/***************************************************************************//**
* \file cyreg_tcpwm.h
*
* \brief
* TCPWM register definition header
*
* \note
* Generator version: 1.6.0.217
* Database revision: TVIIBE4M_WW2014_BTO
*
********************************************************************************
* \copyright
* Copyright 2016-2020, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
*******************************************************************************/

#ifndef _CYREG_TCPWM_H_
#define _CYREG_TCPWM_H_

#include "cyip_tcpwm_v2.h"

/**
  * \brief Timer/Counter/PWM Counter Module (TCPWM_GRP_CNT0)
  */
#define CYREG_TCPWM0_GRP0_CNT0_CTRL     ((volatile un_TCPWM_GRP_CNT_CTRL_t*) 0x40380000UL)
#define CYREG_TCPWM0_GRP0_CNT0_STATUS   ((volatile un_TCPWM_GRP_CNT_STATUS_t*) 0x40380004UL)
#define CYREG_TCPWM0_GRP0_CNT0_COUNTER  ((volatile un_TCPWM_GRP_CNT_COUNTER_t*) 0x40380008UL)
#define CYREG_TCPWM0_GRP0_CNT0_CC0      ((volatile un_TCPWM_GRP_CNT_CC0_t*) 0x40380010UL)
#define CYREG_TCPWM0_GRP0_CNT0_CC0_BUFF ((volatile un_TCPWM_GRP_CNT_CC0_BUFF_t*) 0x40380014UL)
#define CYREG_TCPWM0_GRP0_CNT0_CC1      ((volatile un_TCPWM_GRP_CNT_CC1_t*) 0x40380018UL)
#define CYREG_TCPWM0_GRP0_CNT0_CC1_BUFF ((volatile un_TCPWM_GRP_CNT_CC1_BUFF_t*) 0x4038001CUL)
#define CYREG_TCPWM0_GRP0_CNT0_PERIOD   ((volatile un_TCPWM_GRP_CNT_PERIOD_t*) 0x40380020UL)
#define CYREG_TCPWM0_GRP0_CNT0_PERIOD_BUFF ((volatile un_TCPWM_GRP_CNT_PERIOD_BUFF_t*) 0x40380024UL)
#define CYREG_TCPWM0_GRP0_CNT0_DT       ((volatile un_TCPWM_GRP_CNT_DT_t*) 0x40380030UL)
#define CYREG_TCPWM0_GRP0_CNT0_TR_CMD   ((volatile un_TCPWM_GRP_CNT_TR_CMD_t*) 0x40380040UL)
#define CYREG_TCPWM0_GRP0_CNT0_TR_IN_SEL0 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL0_t*) 0x40380044UL)
#define CYREG_TCPWM0_GRP0_CNT0_TR_IN_SEL1 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL1_t*) 0x40380048UL)
#define CYREG_TCPWM0_GRP0_CNT0_TR_IN_EDGE_SEL ((volatile un_TCPWM_GRP_CNT_TR_IN_EDGE_SEL_t*) 0x4038004CUL)
#define CYREG_TCPWM0_GRP0_CNT0_TR_PWM_CTRL ((volatile un_TCPWM_GRP_CNT_TR_PWM_CTRL_t*) 0x40380050UL)
#define CYREG_TCPWM0_GRP0_CNT0_TR_OUT_SEL ((volatile un_TCPWM_GRP_CNT_TR_OUT_SEL_t*) 0x40380054UL)
#define CYREG_TCPWM0_GRP0_CNT0_INTR     ((volatile un_TCPWM_GRP_CNT_INTR_t*) 0x40380070UL)
#define CYREG_TCPWM0_GRP0_CNT0_INTR_SET ((volatile un_TCPWM_GRP_CNT_INTR_SET_t*) 0x40380074UL)
#define CYREG_TCPWM0_GRP0_CNT0_INTR_MASK ((volatile un_TCPWM_GRP_CNT_INTR_MASK_t*) 0x40380078UL)
#define CYREG_TCPWM0_GRP0_CNT0_INTR_MASKED ((volatile un_TCPWM_GRP_CNT_INTR_MASKED_t*) 0x4038007CUL)

/**
  * \brief Timer/Counter/PWM Counter Module (TCPWM_GRP_CNT1)
  */
#define CYREG_TCPWM0_GRP0_CNT1_CTRL     ((volatile un_TCPWM_GRP_CNT_CTRL_t*) 0x40380080UL)
#define CYREG_TCPWM0_GRP0_CNT1_STATUS   ((volatile un_TCPWM_GRP_CNT_STATUS_t*) 0x40380084UL)
#define CYREG_TCPWM0_GRP0_CNT1_COUNTER  ((volatile un_TCPWM_GRP_CNT_COUNTER_t*) 0x40380088UL)
#define CYREG_TCPWM0_GRP0_CNT1_CC0      ((volatile un_TCPWM_GRP_CNT_CC0_t*) 0x40380090UL)
#define CYREG_TCPWM0_GRP0_CNT1_CC0_BUFF ((volatile un_TCPWM_GRP_CNT_CC0_BUFF_t*) 0x40380094UL)
#define CYREG_TCPWM0_GRP0_CNT1_CC1      ((volatile un_TCPWM_GRP_CNT_CC1_t*) 0x40380098UL)
#define CYREG_TCPWM0_GRP0_CNT1_CC1_BUFF ((volatile un_TCPWM_GRP_CNT_CC1_BUFF_t*) 0x4038009CUL)
#define CYREG_TCPWM0_GRP0_CNT1_PERIOD   ((volatile un_TCPWM_GRP_CNT_PERIOD_t*) 0x403800A0UL)
#define CYREG_TCPWM0_GRP0_CNT1_PERIOD_BUFF ((volatile un_TCPWM_GRP_CNT_PERIOD_BUFF_t*) 0x403800A4UL)
#define CYREG_TCPWM0_GRP0_CNT1_DT       ((volatile un_TCPWM_GRP_CNT_DT_t*) 0x403800B0UL)
#define CYREG_TCPWM0_GRP0_CNT1_TR_CMD   ((volatile un_TCPWM_GRP_CNT_TR_CMD_t*) 0x403800C0UL)
#define CYREG_TCPWM0_GRP0_CNT1_TR_IN_SEL0 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL0_t*) 0x403800C4UL)
#define CYREG_TCPWM0_GRP0_CNT1_TR_IN_SEL1 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL1_t*) 0x403800C8UL)
#define CYREG_TCPWM0_GRP0_CNT1_TR_IN_EDGE_SEL ((volatile un_TCPWM_GRP_CNT_TR_IN_EDGE_SEL_t*) 0x403800CCUL)
#define CYREG_TCPWM0_GRP0_CNT1_TR_PWM_CTRL ((volatile un_TCPWM_GRP_CNT_TR_PWM_CTRL_t*) 0x403800D0UL)
#define CYREG_TCPWM0_GRP0_CNT1_TR_OUT_SEL ((volatile un_TCPWM_GRP_CNT_TR_OUT_SEL_t*) 0x403800D4UL)
#define CYREG_TCPWM0_GRP0_CNT1_INTR     ((volatile un_TCPWM_GRP_CNT_INTR_t*) 0x403800F0UL)
#define CYREG_TCPWM0_GRP0_CNT1_INTR_SET ((volatile un_TCPWM_GRP_CNT_INTR_SET_t*) 0x403800F4UL)
#define CYREG_TCPWM0_GRP0_CNT1_INTR_MASK ((volatile un_TCPWM_GRP_CNT_INTR_MASK_t*) 0x403800F8UL)
#define CYREG_TCPWM0_GRP0_CNT1_INTR_MASKED ((volatile un_TCPWM_GRP_CNT_INTR_MASKED_t*) 0x403800FCUL)

/**
  * \brief Timer/Counter/PWM Counter Module (TCPWM_GRP_CNT2)
  */
#define CYREG_TCPWM0_GRP0_CNT2_CTRL     ((volatile un_TCPWM_GRP_CNT_CTRL_t*) 0x40380100UL)
#define CYREG_TCPWM0_GRP0_CNT2_STATUS   ((volatile un_TCPWM_GRP_CNT_STATUS_t*) 0x40380104UL)
#define CYREG_TCPWM0_GRP0_CNT2_COUNTER  ((volatile un_TCPWM_GRP_CNT_COUNTER_t*) 0x40380108UL)
#define CYREG_TCPWM0_GRP0_CNT2_CC0      ((volatile un_TCPWM_GRP_CNT_CC0_t*) 0x40380110UL)
#define CYREG_TCPWM0_GRP0_CNT2_CC0_BUFF ((volatile un_TCPWM_GRP_CNT_CC0_BUFF_t*) 0x40380114UL)
#define CYREG_TCPWM0_GRP0_CNT2_CC1      ((volatile un_TCPWM_GRP_CNT_CC1_t*) 0x40380118UL)
#define CYREG_TCPWM0_GRP0_CNT2_CC1_BUFF ((volatile un_TCPWM_GRP_CNT_CC1_BUFF_t*) 0x4038011CUL)
#define CYREG_TCPWM0_GRP0_CNT2_PERIOD   ((volatile un_TCPWM_GRP_CNT_PERIOD_t*) 0x40380120UL)
#define CYREG_TCPWM0_GRP0_CNT2_PERIOD_BUFF ((volatile un_TCPWM_GRP_CNT_PERIOD_BUFF_t*) 0x40380124UL)
#define CYREG_TCPWM0_GRP0_CNT2_DT       ((volatile un_TCPWM_GRP_CNT_DT_t*) 0x40380130UL)
#define CYREG_TCPWM0_GRP0_CNT2_TR_CMD   ((volatile un_TCPWM_GRP_CNT_TR_CMD_t*) 0x40380140UL)
#define CYREG_TCPWM0_GRP0_CNT2_TR_IN_SEL0 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL0_t*) 0x40380144UL)
#define CYREG_TCPWM0_GRP0_CNT2_TR_IN_SEL1 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL1_t*) 0x40380148UL)
#define CYREG_TCPWM0_GRP0_CNT2_TR_IN_EDGE_SEL ((volatile un_TCPWM_GRP_CNT_TR_IN_EDGE_SEL_t*) 0x4038014CUL)
#define CYREG_TCPWM0_GRP0_CNT2_TR_PWM_CTRL ((volatile un_TCPWM_GRP_CNT_TR_PWM_CTRL_t*) 0x40380150UL)
#define CYREG_TCPWM0_GRP0_CNT2_TR_OUT_SEL ((volatile un_TCPWM_GRP_CNT_TR_OUT_SEL_t*) 0x40380154UL)
#define CYREG_TCPWM0_GRP0_CNT2_INTR     ((volatile un_TCPWM_GRP_CNT_INTR_t*) 0x40380170UL)
#define CYREG_TCPWM0_GRP0_CNT2_INTR_SET ((volatile un_TCPWM_GRP_CNT_INTR_SET_t*) 0x40380174UL)
#define CYREG_TCPWM0_GRP0_CNT2_INTR_MASK ((volatile un_TCPWM_GRP_CNT_INTR_MASK_t*) 0x40380178UL)
#define CYREG_TCPWM0_GRP0_CNT2_INTR_MASKED ((volatile un_TCPWM_GRP_CNT_INTR_MASKED_t*) 0x4038017CUL)

/**
  * \brief Timer/Counter/PWM Counter Module (TCPWM_GRP_CNT3)
  */
#define CYREG_TCPWM0_GRP0_CNT3_CTRL     ((volatile un_TCPWM_GRP_CNT_CTRL_t*) 0x40380180UL)
#define CYREG_TCPWM0_GRP0_CNT3_STATUS   ((volatile un_TCPWM_GRP_CNT_STATUS_t*) 0x40380184UL)
#define CYREG_TCPWM0_GRP0_CNT3_COUNTER  ((volatile un_TCPWM_GRP_CNT_COUNTER_t*) 0x40380188UL)
#define CYREG_TCPWM0_GRP0_CNT3_CC0      ((volatile un_TCPWM_GRP_CNT_CC0_t*) 0x40380190UL)
#define CYREG_TCPWM0_GRP0_CNT3_CC0_BUFF ((volatile un_TCPWM_GRP_CNT_CC0_BUFF_t*) 0x40380194UL)
#define CYREG_TCPWM0_GRP0_CNT3_CC1      ((volatile un_TCPWM_GRP_CNT_CC1_t*) 0x40380198UL)
#define CYREG_TCPWM0_GRP0_CNT3_CC1_BUFF ((volatile un_TCPWM_GRP_CNT_CC1_BUFF_t*) 0x4038019CUL)
#define CYREG_TCPWM0_GRP0_CNT3_PERIOD   ((volatile un_TCPWM_GRP_CNT_PERIOD_t*) 0x403801A0UL)
#define CYREG_TCPWM0_GRP0_CNT3_PERIOD_BUFF ((volatile un_TCPWM_GRP_CNT_PERIOD_BUFF_t*) 0x403801A4UL)
#define CYREG_TCPWM0_GRP0_CNT3_DT       ((volatile un_TCPWM_GRP_CNT_DT_t*) 0x403801B0UL)
#define CYREG_TCPWM0_GRP0_CNT3_TR_CMD   ((volatile un_TCPWM_GRP_CNT_TR_CMD_t*) 0x403801C0UL)
#define CYREG_TCPWM0_GRP0_CNT3_TR_IN_SEL0 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL0_t*) 0x403801C4UL)
#define CYREG_TCPWM0_GRP0_CNT3_TR_IN_SEL1 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL1_t*) 0x403801C8UL)
#define CYREG_TCPWM0_GRP0_CNT3_TR_IN_EDGE_SEL ((volatile un_TCPWM_GRP_CNT_TR_IN_EDGE_SEL_t*) 0x403801CCUL)
#define CYREG_TCPWM0_GRP0_CNT3_TR_PWM_CTRL ((volatile un_TCPWM_GRP_CNT_TR_PWM_CTRL_t*) 0x403801D0UL)
#define CYREG_TCPWM0_GRP0_CNT3_TR_OUT_SEL ((volatile un_TCPWM_GRP_CNT_TR_OUT_SEL_t*) 0x403801D4UL)
#define CYREG_TCPWM0_GRP0_CNT3_INTR     ((volatile un_TCPWM_GRP_CNT_INTR_t*) 0x403801F0UL)
#define CYREG_TCPWM0_GRP0_CNT3_INTR_SET ((volatile un_TCPWM_GRP_CNT_INTR_SET_t*) 0x403801F4UL)
#define CYREG_TCPWM0_GRP0_CNT3_INTR_MASK ((volatile un_TCPWM_GRP_CNT_INTR_MASK_t*) 0x403801F8UL)
#define CYREG_TCPWM0_GRP0_CNT3_INTR_MASKED ((volatile un_TCPWM_GRP_CNT_INTR_MASKED_t*) 0x403801FCUL)

/**
  * \brief Timer/Counter/PWM Counter Module (TCPWM_GRP_CNT4)
  */
#define CYREG_TCPWM0_GRP0_CNT4_CTRL     ((volatile un_TCPWM_GRP_CNT_CTRL_t*) 0x40380200UL)
#define CYREG_TCPWM0_GRP0_CNT4_STATUS   ((volatile un_TCPWM_GRP_CNT_STATUS_t*) 0x40380204UL)
#define CYREG_TCPWM0_GRP0_CNT4_COUNTER  ((volatile un_TCPWM_GRP_CNT_COUNTER_t*) 0x40380208UL)
#define CYREG_TCPWM0_GRP0_CNT4_CC0      ((volatile un_TCPWM_GRP_CNT_CC0_t*) 0x40380210UL)
#define CYREG_TCPWM0_GRP0_CNT4_CC0_BUFF ((volatile un_TCPWM_GRP_CNT_CC0_BUFF_t*) 0x40380214UL)
#define CYREG_TCPWM0_GRP0_CNT4_CC1      ((volatile un_TCPWM_GRP_CNT_CC1_t*) 0x40380218UL)
#define CYREG_TCPWM0_GRP0_CNT4_CC1_BUFF ((volatile un_TCPWM_GRP_CNT_CC1_BUFF_t*) 0x4038021CUL)
#define CYREG_TCPWM0_GRP0_CNT4_PERIOD   ((volatile un_TCPWM_GRP_CNT_PERIOD_t*) 0x40380220UL)
#define CYREG_TCPWM0_GRP0_CNT4_PERIOD_BUFF ((volatile un_TCPWM_GRP_CNT_PERIOD_BUFF_t*) 0x40380224UL)
#define CYREG_TCPWM0_GRP0_CNT4_DT       ((volatile un_TCPWM_GRP_CNT_DT_t*) 0x40380230UL)
#define CYREG_TCPWM0_GRP0_CNT4_TR_CMD   ((volatile un_TCPWM_GRP_CNT_TR_CMD_t*) 0x40380240UL)
#define CYREG_TCPWM0_GRP0_CNT4_TR_IN_SEL0 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL0_t*) 0x40380244UL)
#define CYREG_TCPWM0_GRP0_CNT4_TR_IN_SEL1 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL1_t*) 0x40380248UL)
#define CYREG_TCPWM0_GRP0_CNT4_TR_IN_EDGE_SEL ((volatile un_TCPWM_GRP_CNT_TR_IN_EDGE_SEL_t*) 0x4038024CUL)
#define CYREG_TCPWM0_GRP0_CNT4_TR_PWM_CTRL ((volatile un_TCPWM_GRP_CNT_TR_PWM_CTRL_t*) 0x40380250UL)
#define CYREG_TCPWM0_GRP0_CNT4_TR_OUT_SEL ((volatile un_TCPWM_GRP_CNT_TR_OUT_SEL_t*) 0x40380254UL)
#define CYREG_TCPWM0_GRP0_CNT4_INTR     ((volatile un_TCPWM_GRP_CNT_INTR_t*) 0x40380270UL)
#define CYREG_TCPWM0_GRP0_CNT4_INTR_SET ((volatile un_TCPWM_GRP_CNT_INTR_SET_t*) 0x40380274UL)
#define CYREG_TCPWM0_GRP0_CNT4_INTR_MASK ((volatile un_TCPWM_GRP_CNT_INTR_MASK_t*) 0x40380278UL)
#define CYREG_TCPWM0_GRP0_CNT4_INTR_MASKED ((volatile un_TCPWM_GRP_CNT_INTR_MASKED_t*) 0x4038027CUL)

/**
  * \brief Timer/Counter/PWM Counter Module (TCPWM_GRP_CNT5)
  */
#define CYREG_TCPWM0_GRP0_CNT5_CTRL     ((volatile un_TCPWM_GRP_CNT_CTRL_t*) 0x40380280UL)
#define CYREG_TCPWM0_GRP0_CNT5_STATUS   ((volatile un_TCPWM_GRP_CNT_STATUS_t*) 0x40380284UL)
#define CYREG_TCPWM0_GRP0_CNT5_COUNTER  ((volatile un_TCPWM_GRP_CNT_COUNTER_t*) 0x40380288UL)
#define CYREG_TCPWM0_GRP0_CNT5_CC0      ((volatile un_TCPWM_GRP_CNT_CC0_t*) 0x40380290UL)
#define CYREG_TCPWM0_GRP0_CNT5_CC0_BUFF ((volatile un_TCPWM_GRP_CNT_CC0_BUFF_t*) 0x40380294UL)
#define CYREG_TCPWM0_GRP0_CNT5_CC1      ((volatile un_TCPWM_GRP_CNT_CC1_t*) 0x40380298UL)
#define CYREG_TCPWM0_GRP0_CNT5_CC1_BUFF ((volatile un_TCPWM_GRP_CNT_CC1_BUFF_t*) 0x4038029CUL)
#define CYREG_TCPWM0_GRP0_CNT5_PERIOD   ((volatile un_TCPWM_GRP_CNT_PERIOD_t*) 0x403802A0UL)
#define CYREG_TCPWM0_GRP0_CNT5_PERIOD_BUFF ((volatile un_TCPWM_GRP_CNT_PERIOD_BUFF_t*) 0x403802A4UL)
#define CYREG_TCPWM0_GRP0_CNT5_DT       ((volatile un_TCPWM_GRP_CNT_DT_t*) 0x403802B0UL)
#define CYREG_TCPWM0_GRP0_CNT5_TR_CMD   ((volatile un_TCPWM_GRP_CNT_TR_CMD_t*) 0x403802C0UL)
#define CYREG_TCPWM0_GRP0_CNT5_TR_IN_SEL0 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL0_t*) 0x403802C4UL)
#define CYREG_TCPWM0_GRP0_CNT5_TR_IN_SEL1 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL1_t*) 0x403802C8UL)
#define CYREG_TCPWM0_GRP0_CNT5_TR_IN_EDGE_SEL ((volatile un_TCPWM_GRP_CNT_TR_IN_EDGE_SEL_t*) 0x403802CCUL)
#define CYREG_TCPWM0_GRP0_CNT5_TR_PWM_CTRL ((volatile un_TCPWM_GRP_CNT_TR_PWM_CTRL_t*) 0x403802D0UL)
#define CYREG_TCPWM0_GRP0_CNT5_TR_OUT_SEL ((volatile un_TCPWM_GRP_CNT_TR_OUT_SEL_t*) 0x403802D4UL)
#define CYREG_TCPWM0_GRP0_CNT5_INTR     ((volatile un_TCPWM_GRP_CNT_INTR_t*) 0x403802F0UL)
#define CYREG_TCPWM0_GRP0_CNT5_INTR_SET ((volatile un_TCPWM_GRP_CNT_INTR_SET_t*) 0x403802F4UL)
#define CYREG_TCPWM0_GRP0_CNT5_INTR_MASK ((volatile un_TCPWM_GRP_CNT_INTR_MASK_t*) 0x403802F8UL)
#define CYREG_TCPWM0_GRP0_CNT5_INTR_MASKED ((volatile un_TCPWM_GRP_CNT_INTR_MASKED_t*) 0x403802FCUL)

/**
  * \brief Timer/Counter/PWM Counter Module (TCPWM_GRP_CNT6)
  */
#define CYREG_TCPWM0_GRP0_CNT6_CTRL     ((volatile un_TCPWM_GRP_CNT_CTRL_t*) 0x40380300UL)
#define CYREG_TCPWM0_GRP0_CNT6_STATUS   ((volatile un_TCPWM_GRP_CNT_STATUS_t*) 0x40380304UL)
#define CYREG_TCPWM0_GRP0_CNT6_COUNTER  ((volatile un_TCPWM_GRP_CNT_COUNTER_t*) 0x40380308UL)
#define CYREG_TCPWM0_GRP0_CNT6_CC0      ((volatile un_TCPWM_GRP_CNT_CC0_t*) 0x40380310UL)
#define CYREG_TCPWM0_GRP0_CNT6_CC0_BUFF ((volatile un_TCPWM_GRP_CNT_CC0_BUFF_t*) 0x40380314UL)
#define CYREG_TCPWM0_GRP0_CNT6_CC1      ((volatile un_TCPWM_GRP_CNT_CC1_t*) 0x40380318UL)
#define CYREG_TCPWM0_GRP0_CNT6_CC1_BUFF ((volatile un_TCPWM_GRP_CNT_CC1_BUFF_t*) 0x4038031CUL)
#define CYREG_TCPWM0_GRP0_CNT6_PERIOD   ((volatile un_TCPWM_GRP_CNT_PERIOD_t*) 0x40380320UL)
#define CYREG_TCPWM0_GRP0_CNT6_PERIOD_BUFF ((volatile un_TCPWM_GRP_CNT_PERIOD_BUFF_t*) 0x40380324UL)
#define CYREG_TCPWM0_GRP0_CNT6_DT       ((volatile un_TCPWM_GRP_CNT_DT_t*) 0x40380330UL)
#define CYREG_TCPWM0_GRP0_CNT6_TR_CMD   ((volatile un_TCPWM_GRP_CNT_TR_CMD_t*) 0x40380340UL)
#define CYREG_TCPWM0_GRP0_CNT6_TR_IN_SEL0 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL0_t*) 0x40380344UL)
#define CYREG_TCPWM0_GRP0_CNT6_TR_IN_SEL1 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL1_t*) 0x40380348UL)
#define CYREG_TCPWM0_GRP0_CNT6_TR_IN_EDGE_SEL ((volatile un_TCPWM_GRP_CNT_TR_IN_EDGE_SEL_t*) 0x4038034CUL)
#define CYREG_TCPWM0_GRP0_CNT6_TR_PWM_CTRL ((volatile un_TCPWM_GRP_CNT_TR_PWM_CTRL_t*) 0x40380350UL)
#define CYREG_TCPWM0_GRP0_CNT6_TR_OUT_SEL ((volatile un_TCPWM_GRP_CNT_TR_OUT_SEL_t*) 0x40380354UL)
#define CYREG_TCPWM0_GRP0_CNT6_INTR     ((volatile un_TCPWM_GRP_CNT_INTR_t*) 0x40380370UL)
#define CYREG_TCPWM0_GRP0_CNT6_INTR_SET ((volatile un_TCPWM_GRP_CNT_INTR_SET_t*) 0x40380374UL)
#define CYREG_TCPWM0_GRP0_CNT6_INTR_MASK ((volatile un_TCPWM_GRP_CNT_INTR_MASK_t*) 0x40380378UL)
#define CYREG_TCPWM0_GRP0_CNT6_INTR_MASKED ((volatile un_TCPWM_GRP_CNT_INTR_MASKED_t*) 0x4038037CUL)

/**
  * \brief Timer/Counter/PWM Counter Module (TCPWM_GRP_CNT7)
  */
#define CYREG_TCPWM0_GRP0_CNT7_CTRL     ((volatile un_TCPWM_GRP_CNT_CTRL_t*) 0x40380380UL)
#define CYREG_TCPWM0_GRP0_CNT7_STATUS   ((volatile un_TCPWM_GRP_CNT_STATUS_t*) 0x40380384UL)
#define CYREG_TCPWM0_GRP0_CNT7_COUNTER  ((volatile un_TCPWM_GRP_CNT_COUNTER_t*) 0x40380388UL)
#define CYREG_TCPWM0_GRP0_CNT7_CC0      ((volatile un_TCPWM_GRP_CNT_CC0_t*) 0x40380390UL)
#define CYREG_TCPWM0_GRP0_CNT7_CC0_BUFF ((volatile un_TCPWM_GRP_CNT_CC0_BUFF_t*) 0x40380394UL)
#define CYREG_TCPWM0_GRP0_CNT7_CC1      ((volatile un_TCPWM_GRP_CNT_CC1_t*) 0x40380398UL)
#define CYREG_TCPWM0_GRP0_CNT7_CC1_BUFF ((volatile un_TCPWM_GRP_CNT_CC1_BUFF_t*) 0x4038039CUL)
#define CYREG_TCPWM0_GRP0_CNT7_PERIOD   ((volatile un_TCPWM_GRP_CNT_PERIOD_t*) 0x403803A0UL)
#define CYREG_TCPWM0_GRP0_CNT7_PERIOD_BUFF ((volatile un_TCPWM_GRP_CNT_PERIOD_BUFF_t*) 0x403803A4UL)
#define CYREG_TCPWM0_GRP0_CNT7_DT       ((volatile un_TCPWM_GRP_CNT_DT_t*) 0x403803B0UL)
#define CYREG_TCPWM0_GRP0_CNT7_TR_CMD   ((volatile un_TCPWM_GRP_CNT_TR_CMD_t*) 0x403803C0UL)
#define CYREG_TCPWM0_GRP0_CNT7_TR_IN_SEL0 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL0_t*) 0x403803C4UL)
#define CYREG_TCPWM0_GRP0_CNT7_TR_IN_SEL1 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL1_t*) 0x403803C8UL)
#define CYREG_TCPWM0_GRP0_CNT7_TR_IN_EDGE_SEL ((volatile un_TCPWM_GRP_CNT_TR_IN_EDGE_SEL_t*) 0x403803CCUL)
#define CYREG_TCPWM0_GRP0_CNT7_TR_PWM_CTRL ((volatile un_TCPWM_GRP_CNT_TR_PWM_CTRL_t*) 0x403803D0UL)
#define CYREG_TCPWM0_GRP0_CNT7_TR_OUT_SEL ((volatile un_TCPWM_GRP_CNT_TR_OUT_SEL_t*) 0x403803D4UL)
#define CYREG_TCPWM0_GRP0_CNT7_INTR     ((volatile un_TCPWM_GRP_CNT_INTR_t*) 0x403803F0UL)
#define CYREG_TCPWM0_GRP0_CNT7_INTR_SET ((volatile un_TCPWM_GRP_CNT_INTR_SET_t*) 0x403803F4UL)
#define CYREG_TCPWM0_GRP0_CNT7_INTR_MASK ((volatile un_TCPWM_GRP_CNT_INTR_MASK_t*) 0x403803F8UL)
#define CYREG_TCPWM0_GRP0_CNT7_INTR_MASKED ((volatile un_TCPWM_GRP_CNT_INTR_MASKED_t*) 0x403803FCUL)

/**
  * \brief Timer/Counter/PWM Counter Module (TCPWM_GRP_CNT8)
  */
#define CYREG_TCPWM0_GRP0_CNT8_CTRL     ((volatile un_TCPWM_GRP_CNT_CTRL_t*) 0x40380400UL)
#define CYREG_TCPWM0_GRP0_CNT8_STATUS   ((volatile un_TCPWM_GRP_CNT_STATUS_t*) 0x40380404UL)
#define CYREG_TCPWM0_GRP0_CNT8_COUNTER  ((volatile un_TCPWM_GRP_CNT_COUNTER_t*) 0x40380408UL)
#define CYREG_TCPWM0_GRP0_CNT8_CC0      ((volatile un_TCPWM_GRP_CNT_CC0_t*) 0x40380410UL)
#define CYREG_TCPWM0_GRP0_CNT8_CC0_BUFF ((volatile un_TCPWM_GRP_CNT_CC0_BUFF_t*) 0x40380414UL)
#define CYREG_TCPWM0_GRP0_CNT8_CC1      ((volatile un_TCPWM_GRP_CNT_CC1_t*) 0x40380418UL)
#define CYREG_TCPWM0_GRP0_CNT8_CC1_BUFF ((volatile un_TCPWM_GRP_CNT_CC1_BUFF_t*) 0x4038041CUL)
#define CYREG_TCPWM0_GRP0_CNT8_PERIOD   ((volatile un_TCPWM_GRP_CNT_PERIOD_t*) 0x40380420UL)
#define CYREG_TCPWM0_GRP0_CNT8_PERIOD_BUFF ((volatile un_TCPWM_GRP_CNT_PERIOD_BUFF_t*) 0x40380424UL)
#define CYREG_TCPWM0_GRP0_CNT8_DT       ((volatile un_TCPWM_GRP_CNT_DT_t*) 0x40380430UL)
#define CYREG_TCPWM0_GRP0_CNT8_TR_CMD   ((volatile un_TCPWM_GRP_CNT_TR_CMD_t*) 0x40380440UL)
#define CYREG_TCPWM0_GRP0_CNT8_TR_IN_SEL0 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL0_t*) 0x40380444UL)
#define CYREG_TCPWM0_GRP0_CNT8_TR_IN_SEL1 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL1_t*) 0x40380448UL)
#define CYREG_TCPWM0_GRP0_CNT8_TR_IN_EDGE_SEL ((volatile un_TCPWM_GRP_CNT_TR_IN_EDGE_SEL_t*) 0x4038044CUL)
#define CYREG_TCPWM0_GRP0_CNT8_TR_PWM_CTRL ((volatile un_TCPWM_GRP_CNT_TR_PWM_CTRL_t*) 0x40380450UL)
#define CYREG_TCPWM0_GRP0_CNT8_TR_OUT_SEL ((volatile un_TCPWM_GRP_CNT_TR_OUT_SEL_t*) 0x40380454UL)
#define CYREG_TCPWM0_GRP0_CNT8_INTR     ((volatile un_TCPWM_GRP_CNT_INTR_t*) 0x40380470UL)
#define CYREG_TCPWM0_GRP0_CNT8_INTR_SET ((volatile un_TCPWM_GRP_CNT_INTR_SET_t*) 0x40380474UL)
#define CYREG_TCPWM0_GRP0_CNT8_INTR_MASK ((volatile un_TCPWM_GRP_CNT_INTR_MASK_t*) 0x40380478UL)
#define CYREG_TCPWM0_GRP0_CNT8_INTR_MASKED ((volatile un_TCPWM_GRP_CNT_INTR_MASKED_t*) 0x4038047CUL)

/**
  * \brief Timer/Counter/PWM Counter Module (TCPWM_GRP_CNT9)
  */
#define CYREG_TCPWM0_GRP0_CNT9_CTRL     ((volatile un_TCPWM_GRP_CNT_CTRL_t*) 0x40380480UL)
#define CYREG_TCPWM0_GRP0_CNT9_STATUS   ((volatile un_TCPWM_GRP_CNT_STATUS_t*) 0x40380484UL)
#define CYREG_TCPWM0_GRP0_CNT9_COUNTER  ((volatile un_TCPWM_GRP_CNT_COUNTER_t*) 0x40380488UL)
#define CYREG_TCPWM0_GRP0_CNT9_CC0      ((volatile un_TCPWM_GRP_CNT_CC0_t*) 0x40380490UL)
#define CYREG_TCPWM0_GRP0_CNT9_CC0_BUFF ((volatile un_TCPWM_GRP_CNT_CC0_BUFF_t*) 0x40380494UL)
#define CYREG_TCPWM0_GRP0_CNT9_CC1      ((volatile un_TCPWM_GRP_CNT_CC1_t*) 0x40380498UL)
#define CYREG_TCPWM0_GRP0_CNT9_CC1_BUFF ((volatile un_TCPWM_GRP_CNT_CC1_BUFF_t*) 0x4038049CUL)
#define CYREG_TCPWM0_GRP0_CNT9_PERIOD   ((volatile un_TCPWM_GRP_CNT_PERIOD_t*) 0x403804A0UL)
#define CYREG_TCPWM0_GRP0_CNT9_PERIOD_BUFF ((volatile un_TCPWM_GRP_CNT_PERIOD_BUFF_t*) 0x403804A4UL)
#define CYREG_TCPWM0_GRP0_CNT9_DT       ((volatile un_TCPWM_GRP_CNT_DT_t*) 0x403804B0UL)
#define CYREG_TCPWM0_GRP0_CNT9_TR_CMD   ((volatile un_TCPWM_GRP_CNT_TR_CMD_t*) 0x403804C0UL)
#define CYREG_TCPWM0_GRP0_CNT9_TR_IN_SEL0 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL0_t*) 0x403804C4UL)
#define CYREG_TCPWM0_GRP0_CNT9_TR_IN_SEL1 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL1_t*) 0x403804C8UL)
#define CYREG_TCPWM0_GRP0_CNT9_TR_IN_EDGE_SEL ((volatile un_TCPWM_GRP_CNT_TR_IN_EDGE_SEL_t*) 0x403804CCUL)
#define CYREG_TCPWM0_GRP0_CNT9_TR_PWM_CTRL ((volatile un_TCPWM_GRP_CNT_TR_PWM_CTRL_t*) 0x403804D0UL)
#define CYREG_TCPWM0_GRP0_CNT9_TR_OUT_SEL ((volatile un_TCPWM_GRP_CNT_TR_OUT_SEL_t*) 0x403804D4UL)
#define CYREG_TCPWM0_GRP0_CNT9_INTR     ((volatile un_TCPWM_GRP_CNT_INTR_t*) 0x403804F0UL)
#define CYREG_TCPWM0_GRP0_CNT9_INTR_SET ((volatile un_TCPWM_GRP_CNT_INTR_SET_t*) 0x403804F4UL)
#define CYREG_TCPWM0_GRP0_CNT9_INTR_MASK ((volatile un_TCPWM_GRP_CNT_INTR_MASK_t*) 0x403804F8UL)
#define CYREG_TCPWM0_GRP0_CNT9_INTR_MASKED ((volatile un_TCPWM_GRP_CNT_INTR_MASKED_t*) 0x403804FCUL)

/**
  * \brief Timer/Counter/PWM Counter Module (TCPWM_GRP_CNT10)
  */
#define CYREG_TCPWM0_GRP0_CNT10_CTRL    ((volatile un_TCPWM_GRP_CNT_CTRL_t*) 0x40380500UL)
#define CYREG_TCPWM0_GRP0_CNT10_STATUS  ((volatile un_TCPWM_GRP_CNT_STATUS_t*) 0x40380504UL)
#define CYREG_TCPWM0_GRP0_CNT10_COUNTER ((volatile un_TCPWM_GRP_CNT_COUNTER_t*) 0x40380508UL)
#define CYREG_TCPWM0_GRP0_CNT10_CC0     ((volatile un_TCPWM_GRP_CNT_CC0_t*) 0x40380510UL)
#define CYREG_TCPWM0_GRP0_CNT10_CC0_BUFF ((volatile un_TCPWM_GRP_CNT_CC0_BUFF_t*) 0x40380514UL)
#define CYREG_TCPWM0_GRP0_CNT10_CC1     ((volatile un_TCPWM_GRP_CNT_CC1_t*) 0x40380518UL)
#define CYREG_TCPWM0_GRP0_CNT10_CC1_BUFF ((volatile un_TCPWM_GRP_CNT_CC1_BUFF_t*) 0x4038051CUL)
#define CYREG_TCPWM0_GRP0_CNT10_PERIOD  ((volatile un_TCPWM_GRP_CNT_PERIOD_t*) 0x40380520UL)
#define CYREG_TCPWM0_GRP0_CNT10_PERIOD_BUFF ((volatile un_TCPWM_GRP_CNT_PERIOD_BUFF_t*) 0x40380524UL)
#define CYREG_TCPWM0_GRP0_CNT10_DT      ((volatile un_TCPWM_GRP_CNT_DT_t*) 0x40380530UL)
#define CYREG_TCPWM0_GRP0_CNT10_TR_CMD  ((volatile un_TCPWM_GRP_CNT_TR_CMD_t*) 0x40380540UL)
#define CYREG_TCPWM0_GRP0_CNT10_TR_IN_SEL0 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL0_t*) 0x40380544UL)
#define CYREG_TCPWM0_GRP0_CNT10_TR_IN_SEL1 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL1_t*) 0x40380548UL)
#define CYREG_TCPWM0_GRP0_CNT10_TR_IN_EDGE_SEL ((volatile un_TCPWM_GRP_CNT_TR_IN_EDGE_SEL_t*) 0x4038054CUL)
#define CYREG_TCPWM0_GRP0_CNT10_TR_PWM_CTRL ((volatile un_TCPWM_GRP_CNT_TR_PWM_CTRL_t*) 0x40380550UL)
#define CYREG_TCPWM0_GRP0_CNT10_TR_OUT_SEL ((volatile un_TCPWM_GRP_CNT_TR_OUT_SEL_t*) 0x40380554UL)
#define CYREG_TCPWM0_GRP0_CNT10_INTR    ((volatile un_TCPWM_GRP_CNT_INTR_t*) 0x40380570UL)
#define CYREG_TCPWM0_GRP0_CNT10_INTR_SET ((volatile un_TCPWM_GRP_CNT_INTR_SET_t*) 0x40380574UL)
#define CYREG_TCPWM0_GRP0_CNT10_INTR_MASK ((volatile un_TCPWM_GRP_CNT_INTR_MASK_t*) 0x40380578UL)
#define CYREG_TCPWM0_GRP0_CNT10_INTR_MASKED ((volatile un_TCPWM_GRP_CNT_INTR_MASKED_t*) 0x4038057CUL)

/**
  * \brief Timer/Counter/PWM Counter Module (TCPWM_GRP_CNT11)
  */
#define CYREG_TCPWM0_GRP0_CNT11_CTRL    ((volatile un_TCPWM_GRP_CNT_CTRL_t*) 0x40380580UL)
#define CYREG_TCPWM0_GRP0_CNT11_STATUS  ((volatile un_TCPWM_GRP_CNT_STATUS_t*) 0x40380584UL)
#define CYREG_TCPWM0_GRP0_CNT11_COUNTER ((volatile un_TCPWM_GRP_CNT_COUNTER_t*) 0x40380588UL)
#define CYREG_TCPWM0_GRP0_CNT11_CC0     ((volatile un_TCPWM_GRP_CNT_CC0_t*) 0x40380590UL)
#define CYREG_TCPWM0_GRP0_CNT11_CC0_BUFF ((volatile un_TCPWM_GRP_CNT_CC0_BUFF_t*) 0x40380594UL)
#define CYREG_TCPWM0_GRP0_CNT11_CC1     ((volatile un_TCPWM_GRP_CNT_CC1_t*) 0x40380598UL)
#define CYREG_TCPWM0_GRP0_CNT11_CC1_BUFF ((volatile un_TCPWM_GRP_CNT_CC1_BUFF_t*) 0x4038059CUL)
#define CYREG_TCPWM0_GRP0_CNT11_PERIOD  ((volatile un_TCPWM_GRP_CNT_PERIOD_t*) 0x403805A0UL)
#define CYREG_TCPWM0_GRP0_CNT11_PERIOD_BUFF ((volatile un_TCPWM_GRP_CNT_PERIOD_BUFF_t*) 0x403805A4UL)
#define CYREG_TCPWM0_GRP0_CNT11_DT      ((volatile un_TCPWM_GRP_CNT_DT_t*) 0x403805B0UL)
#define CYREG_TCPWM0_GRP0_CNT11_TR_CMD  ((volatile un_TCPWM_GRP_CNT_TR_CMD_t*) 0x403805C0UL)
#define CYREG_TCPWM0_GRP0_CNT11_TR_IN_SEL0 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL0_t*) 0x403805C4UL)
#define CYREG_TCPWM0_GRP0_CNT11_TR_IN_SEL1 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL1_t*) 0x403805C8UL)
#define CYREG_TCPWM0_GRP0_CNT11_TR_IN_EDGE_SEL ((volatile un_TCPWM_GRP_CNT_TR_IN_EDGE_SEL_t*) 0x403805CCUL)
#define CYREG_TCPWM0_GRP0_CNT11_TR_PWM_CTRL ((volatile un_TCPWM_GRP_CNT_TR_PWM_CTRL_t*) 0x403805D0UL)
#define CYREG_TCPWM0_GRP0_CNT11_TR_OUT_SEL ((volatile un_TCPWM_GRP_CNT_TR_OUT_SEL_t*) 0x403805D4UL)
#define CYREG_TCPWM0_GRP0_CNT11_INTR    ((volatile un_TCPWM_GRP_CNT_INTR_t*) 0x403805F0UL)
#define CYREG_TCPWM0_GRP0_CNT11_INTR_SET ((volatile un_TCPWM_GRP_CNT_INTR_SET_t*) 0x403805F4UL)
#define CYREG_TCPWM0_GRP0_CNT11_INTR_MASK ((volatile un_TCPWM_GRP_CNT_INTR_MASK_t*) 0x403805F8UL)
#define CYREG_TCPWM0_GRP0_CNT11_INTR_MASKED ((volatile un_TCPWM_GRP_CNT_INTR_MASKED_t*) 0x403805FCUL)

/**
  * \brief Timer/Counter/PWM Counter Module (TCPWM_GRP_CNT12)
  */
#define CYREG_TCPWM0_GRP0_CNT12_CTRL    ((volatile un_TCPWM_GRP_CNT_CTRL_t*) 0x40380600UL)
#define CYREG_TCPWM0_GRP0_CNT12_STATUS  ((volatile un_TCPWM_GRP_CNT_STATUS_t*) 0x40380604UL)
#define CYREG_TCPWM0_GRP0_CNT12_COUNTER ((volatile un_TCPWM_GRP_CNT_COUNTER_t*) 0x40380608UL)
#define CYREG_TCPWM0_GRP0_CNT12_CC0     ((volatile un_TCPWM_GRP_CNT_CC0_t*) 0x40380610UL)
#define CYREG_TCPWM0_GRP0_CNT12_CC0_BUFF ((volatile un_TCPWM_GRP_CNT_CC0_BUFF_t*) 0x40380614UL)
#define CYREG_TCPWM0_GRP0_CNT12_CC1     ((volatile un_TCPWM_GRP_CNT_CC1_t*) 0x40380618UL)
#define CYREG_TCPWM0_GRP0_CNT12_CC1_BUFF ((volatile un_TCPWM_GRP_CNT_CC1_BUFF_t*) 0x4038061CUL)
#define CYREG_TCPWM0_GRP0_CNT12_PERIOD  ((volatile un_TCPWM_GRP_CNT_PERIOD_t*) 0x40380620UL)
#define CYREG_TCPWM0_GRP0_CNT12_PERIOD_BUFF ((volatile un_TCPWM_GRP_CNT_PERIOD_BUFF_t*) 0x40380624UL)
#define CYREG_TCPWM0_GRP0_CNT12_DT      ((volatile un_TCPWM_GRP_CNT_DT_t*) 0x40380630UL)
#define CYREG_TCPWM0_GRP0_CNT12_TR_CMD  ((volatile un_TCPWM_GRP_CNT_TR_CMD_t*) 0x40380640UL)
#define CYREG_TCPWM0_GRP0_CNT12_TR_IN_SEL0 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL0_t*) 0x40380644UL)
#define CYREG_TCPWM0_GRP0_CNT12_TR_IN_SEL1 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL1_t*) 0x40380648UL)
#define CYREG_TCPWM0_GRP0_CNT12_TR_IN_EDGE_SEL ((volatile un_TCPWM_GRP_CNT_TR_IN_EDGE_SEL_t*) 0x4038064CUL)
#define CYREG_TCPWM0_GRP0_CNT12_TR_PWM_CTRL ((volatile un_TCPWM_GRP_CNT_TR_PWM_CTRL_t*) 0x40380650UL)
#define CYREG_TCPWM0_GRP0_CNT12_TR_OUT_SEL ((volatile un_TCPWM_GRP_CNT_TR_OUT_SEL_t*) 0x40380654UL)
#define CYREG_TCPWM0_GRP0_CNT12_INTR    ((volatile un_TCPWM_GRP_CNT_INTR_t*) 0x40380670UL)
#define CYREG_TCPWM0_GRP0_CNT12_INTR_SET ((volatile un_TCPWM_GRP_CNT_INTR_SET_t*) 0x40380674UL)
#define CYREG_TCPWM0_GRP0_CNT12_INTR_MASK ((volatile un_TCPWM_GRP_CNT_INTR_MASK_t*) 0x40380678UL)
#define CYREG_TCPWM0_GRP0_CNT12_INTR_MASKED ((volatile un_TCPWM_GRP_CNT_INTR_MASKED_t*) 0x4038067CUL)

/**
  * \brief Timer/Counter/PWM Counter Module (TCPWM_GRP_CNT13)
  */
#define CYREG_TCPWM0_GRP0_CNT13_CTRL    ((volatile un_TCPWM_GRP_CNT_CTRL_t*) 0x40380680UL)
#define CYREG_TCPWM0_GRP0_CNT13_STATUS  ((volatile un_TCPWM_GRP_CNT_STATUS_t*) 0x40380684UL)
#define CYREG_TCPWM0_GRP0_CNT13_COUNTER ((volatile un_TCPWM_GRP_CNT_COUNTER_t*) 0x40380688UL)
#define CYREG_TCPWM0_GRP0_CNT13_CC0     ((volatile un_TCPWM_GRP_CNT_CC0_t*) 0x40380690UL)
#define CYREG_TCPWM0_GRP0_CNT13_CC0_BUFF ((volatile un_TCPWM_GRP_CNT_CC0_BUFF_t*) 0x40380694UL)
#define CYREG_TCPWM0_GRP0_CNT13_CC1     ((volatile un_TCPWM_GRP_CNT_CC1_t*) 0x40380698UL)
#define CYREG_TCPWM0_GRP0_CNT13_CC1_BUFF ((volatile un_TCPWM_GRP_CNT_CC1_BUFF_t*) 0x4038069CUL)
#define CYREG_TCPWM0_GRP0_CNT13_PERIOD  ((volatile un_TCPWM_GRP_CNT_PERIOD_t*) 0x403806A0UL)
#define CYREG_TCPWM0_GRP0_CNT13_PERIOD_BUFF ((volatile un_TCPWM_GRP_CNT_PERIOD_BUFF_t*) 0x403806A4UL)
#define CYREG_TCPWM0_GRP0_CNT13_DT      ((volatile un_TCPWM_GRP_CNT_DT_t*) 0x403806B0UL)
#define CYREG_TCPWM0_GRP0_CNT13_TR_CMD  ((volatile un_TCPWM_GRP_CNT_TR_CMD_t*) 0x403806C0UL)
#define CYREG_TCPWM0_GRP0_CNT13_TR_IN_SEL0 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL0_t*) 0x403806C4UL)
#define CYREG_TCPWM0_GRP0_CNT13_TR_IN_SEL1 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL1_t*) 0x403806C8UL)
#define CYREG_TCPWM0_GRP0_CNT13_TR_IN_EDGE_SEL ((volatile un_TCPWM_GRP_CNT_TR_IN_EDGE_SEL_t*) 0x403806CCUL)
#define CYREG_TCPWM0_GRP0_CNT13_TR_PWM_CTRL ((volatile un_TCPWM_GRP_CNT_TR_PWM_CTRL_t*) 0x403806D0UL)
#define CYREG_TCPWM0_GRP0_CNT13_TR_OUT_SEL ((volatile un_TCPWM_GRP_CNT_TR_OUT_SEL_t*) 0x403806D4UL)
#define CYREG_TCPWM0_GRP0_CNT13_INTR    ((volatile un_TCPWM_GRP_CNT_INTR_t*) 0x403806F0UL)
#define CYREG_TCPWM0_GRP0_CNT13_INTR_SET ((volatile un_TCPWM_GRP_CNT_INTR_SET_t*) 0x403806F4UL)
#define CYREG_TCPWM0_GRP0_CNT13_INTR_MASK ((volatile un_TCPWM_GRP_CNT_INTR_MASK_t*) 0x403806F8UL)
#define CYREG_TCPWM0_GRP0_CNT13_INTR_MASKED ((volatile un_TCPWM_GRP_CNT_INTR_MASKED_t*) 0x403806FCUL)

/**
  * \brief Timer/Counter/PWM Counter Module (TCPWM_GRP_CNT14)
  */
#define CYREG_TCPWM0_GRP0_CNT14_CTRL    ((volatile un_TCPWM_GRP_CNT_CTRL_t*) 0x40380700UL)
#define CYREG_TCPWM0_GRP0_CNT14_STATUS  ((volatile un_TCPWM_GRP_CNT_STATUS_t*) 0x40380704UL)
#define CYREG_TCPWM0_GRP0_CNT14_COUNTER ((volatile un_TCPWM_GRP_CNT_COUNTER_t*) 0x40380708UL)
#define CYREG_TCPWM0_GRP0_CNT14_CC0     ((volatile un_TCPWM_GRP_CNT_CC0_t*) 0x40380710UL)
#define CYREG_TCPWM0_GRP0_CNT14_CC0_BUFF ((volatile un_TCPWM_GRP_CNT_CC0_BUFF_t*) 0x40380714UL)
#define CYREG_TCPWM0_GRP0_CNT14_CC1     ((volatile un_TCPWM_GRP_CNT_CC1_t*) 0x40380718UL)
#define CYREG_TCPWM0_GRP0_CNT14_CC1_BUFF ((volatile un_TCPWM_GRP_CNT_CC1_BUFF_t*) 0x4038071CUL)
#define CYREG_TCPWM0_GRP0_CNT14_PERIOD  ((volatile un_TCPWM_GRP_CNT_PERIOD_t*) 0x40380720UL)
#define CYREG_TCPWM0_GRP0_CNT14_PERIOD_BUFF ((volatile un_TCPWM_GRP_CNT_PERIOD_BUFF_t*) 0x40380724UL)
#define CYREG_TCPWM0_GRP0_CNT14_DT      ((volatile un_TCPWM_GRP_CNT_DT_t*) 0x40380730UL)
#define CYREG_TCPWM0_GRP0_CNT14_TR_CMD  ((volatile un_TCPWM_GRP_CNT_TR_CMD_t*) 0x40380740UL)
#define CYREG_TCPWM0_GRP0_CNT14_TR_IN_SEL0 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL0_t*) 0x40380744UL)
#define CYREG_TCPWM0_GRP0_CNT14_TR_IN_SEL1 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL1_t*) 0x40380748UL)
#define CYREG_TCPWM0_GRP0_CNT14_TR_IN_EDGE_SEL ((volatile un_TCPWM_GRP_CNT_TR_IN_EDGE_SEL_t*) 0x4038074CUL)
#define CYREG_TCPWM0_GRP0_CNT14_TR_PWM_CTRL ((volatile un_TCPWM_GRP_CNT_TR_PWM_CTRL_t*) 0x40380750UL)
#define CYREG_TCPWM0_GRP0_CNT14_TR_OUT_SEL ((volatile un_TCPWM_GRP_CNT_TR_OUT_SEL_t*) 0x40380754UL)
#define CYREG_TCPWM0_GRP0_CNT14_INTR    ((volatile un_TCPWM_GRP_CNT_INTR_t*) 0x40380770UL)
#define CYREG_TCPWM0_GRP0_CNT14_INTR_SET ((volatile un_TCPWM_GRP_CNT_INTR_SET_t*) 0x40380774UL)
#define CYREG_TCPWM0_GRP0_CNT14_INTR_MASK ((volatile un_TCPWM_GRP_CNT_INTR_MASK_t*) 0x40380778UL)
#define CYREG_TCPWM0_GRP0_CNT14_INTR_MASKED ((volatile un_TCPWM_GRP_CNT_INTR_MASKED_t*) 0x4038077CUL)

/**
  * \brief Timer/Counter/PWM Counter Module (TCPWM_GRP_CNT15)
  */
#define CYREG_TCPWM0_GRP0_CNT15_CTRL    ((volatile un_TCPWM_GRP_CNT_CTRL_t*) 0x40380780UL)
#define CYREG_TCPWM0_GRP0_CNT15_STATUS  ((volatile un_TCPWM_GRP_CNT_STATUS_t*) 0x40380784UL)
#define CYREG_TCPWM0_GRP0_CNT15_COUNTER ((volatile un_TCPWM_GRP_CNT_COUNTER_t*) 0x40380788UL)
#define CYREG_TCPWM0_GRP0_CNT15_CC0     ((volatile un_TCPWM_GRP_CNT_CC0_t*) 0x40380790UL)
#define CYREG_TCPWM0_GRP0_CNT15_CC0_BUFF ((volatile un_TCPWM_GRP_CNT_CC0_BUFF_t*) 0x40380794UL)
#define CYREG_TCPWM0_GRP0_CNT15_CC1     ((volatile un_TCPWM_GRP_CNT_CC1_t*) 0x40380798UL)
#define CYREG_TCPWM0_GRP0_CNT15_CC1_BUFF ((volatile un_TCPWM_GRP_CNT_CC1_BUFF_t*) 0x4038079CUL)
#define CYREG_TCPWM0_GRP0_CNT15_PERIOD  ((volatile un_TCPWM_GRP_CNT_PERIOD_t*) 0x403807A0UL)
#define CYREG_TCPWM0_GRP0_CNT15_PERIOD_BUFF ((volatile un_TCPWM_GRP_CNT_PERIOD_BUFF_t*) 0x403807A4UL)
#define CYREG_TCPWM0_GRP0_CNT15_DT      ((volatile un_TCPWM_GRP_CNT_DT_t*) 0x403807B0UL)
#define CYREG_TCPWM0_GRP0_CNT15_TR_CMD  ((volatile un_TCPWM_GRP_CNT_TR_CMD_t*) 0x403807C0UL)
#define CYREG_TCPWM0_GRP0_CNT15_TR_IN_SEL0 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL0_t*) 0x403807C4UL)
#define CYREG_TCPWM0_GRP0_CNT15_TR_IN_SEL1 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL1_t*) 0x403807C8UL)
#define CYREG_TCPWM0_GRP0_CNT15_TR_IN_EDGE_SEL ((volatile un_TCPWM_GRP_CNT_TR_IN_EDGE_SEL_t*) 0x403807CCUL)
#define CYREG_TCPWM0_GRP0_CNT15_TR_PWM_CTRL ((volatile un_TCPWM_GRP_CNT_TR_PWM_CTRL_t*) 0x403807D0UL)
#define CYREG_TCPWM0_GRP0_CNT15_TR_OUT_SEL ((volatile un_TCPWM_GRP_CNT_TR_OUT_SEL_t*) 0x403807D4UL)
#define CYREG_TCPWM0_GRP0_CNT15_INTR    ((volatile un_TCPWM_GRP_CNT_INTR_t*) 0x403807F0UL)
#define CYREG_TCPWM0_GRP0_CNT15_INTR_SET ((volatile un_TCPWM_GRP_CNT_INTR_SET_t*) 0x403807F4UL)
#define CYREG_TCPWM0_GRP0_CNT15_INTR_MASK ((volatile un_TCPWM_GRP_CNT_INTR_MASK_t*) 0x403807F8UL)
#define CYREG_TCPWM0_GRP0_CNT15_INTR_MASKED ((volatile un_TCPWM_GRP_CNT_INTR_MASKED_t*) 0x403807FCUL)

/**
  * \brief Timer/Counter/PWM Counter Module (TCPWM_GRP_CNT16)
  */
#define CYREG_TCPWM0_GRP0_CNT16_CTRL    ((volatile un_TCPWM_GRP_CNT_CTRL_t*) 0x40380800UL)
#define CYREG_TCPWM0_GRP0_CNT16_STATUS  ((volatile un_TCPWM_GRP_CNT_STATUS_t*) 0x40380804UL)
#define CYREG_TCPWM0_GRP0_CNT16_COUNTER ((volatile un_TCPWM_GRP_CNT_COUNTER_t*) 0x40380808UL)
#define CYREG_TCPWM0_GRP0_CNT16_CC0     ((volatile un_TCPWM_GRP_CNT_CC0_t*) 0x40380810UL)
#define CYREG_TCPWM0_GRP0_CNT16_CC0_BUFF ((volatile un_TCPWM_GRP_CNT_CC0_BUFF_t*) 0x40380814UL)
#define CYREG_TCPWM0_GRP0_CNT16_CC1     ((volatile un_TCPWM_GRP_CNT_CC1_t*) 0x40380818UL)
#define CYREG_TCPWM0_GRP0_CNT16_CC1_BUFF ((volatile un_TCPWM_GRP_CNT_CC1_BUFF_t*) 0x4038081CUL)
#define CYREG_TCPWM0_GRP0_CNT16_PERIOD  ((volatile un_TCPWM_GRP_CNT_PERIOD_t*) 0x40380820UL)
#define CYREG_TCPWM0_GRP0_CNT16_PERIOD_BUFF ((volatile un_TCPWM_GRP_CNT_PERIOD_BUFF_t*) 0x40380824UL)
#define CYREG_TCPWM0_GRP0_CNT16_DT      ((volatile un_TCPWM_GRP_CNT_DT_t*) 0x40380830UL)
#define CYREG_TCPWM0_GRP0_CNT16_TR_CMD  ((volatile un_TCPWM_GRP_CNT_TR_CMD_t*) 0x40380840UL)
#define CYREG_TCPWM0_GRP0_CNT16_TR_IN_SEL0 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL0_t*) 0x40380844UL)
#define CYREG_TCPWM0_GRP0_CNT16_TR_IN_SEL1 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL1_t*) 0x40380848UL)
#define CYREG_TCPWM0_GRP0_CNT16_TR_IN_EDGE_SEL ((volatile un_TCPWM_GRP_CNT_TR_IN_EDGE_SEL_t*) 0x4038084CUL)
#define CYREG_TCPWM0_GRP0_CNT16_TR_PWM_CTRL ((volatile un_TCPWM_GRP_CNT_TR_PWM_CTRL_t*) 0x40380850UL)
#define CYREG_TCPWM0_GRP0_CNT16_TR_OUT_SEL ((volatile un_TCPWM_GRP_CNT_TR_OUT_SEL_t*) 0x40380854UL)
#define CYREG_TCPWM0_GRP0_CNT16_INTR    ((volatile un_TCPWM_GRP_CNT_INTR_t*) 0x40380870UL)
#define CYREG_TCPWM0_GRP0_CNT16_INTR_SET ((volatile un_TCPWM_GRP_CNT_INTR_SET_t*) 0x40380874UL)
#define CYREG_TCPWM0_GRP0_CNT16_INTR_MASK ((volatile un_TCPWM_GRP_CNT_INTR_MASK_t*) 0x40380878UL)
#define CYREG_TCPWM0_GRP0_CNT16_INTR_MASKED ((volatile un_TCPWM_GRP_CNT_INTR_MASKED_t*) 0x4038087CUL)

/**
  * \brief Timer/Counter/PWM Counter Module (TCPWM_GRP_CNT17)
  */
#define CYREG_TCPWM0_GRP0_CNT17_CTRL    ((volatile un_TCPWM_GRP_CNT_CTRL_t*) 0x40380880UL)
#define CYREG_TCPWM0_GRP0_CNT17_STATUS  ((volatile un_TCPWM_GRP_CNT_STATUS_t*) 0x40380884UL)
#define CYREG_TCPWM0_GRP0_CNT17_COUNTER ((volatile un_TCPWM_GRP_CNT_COUNTER_t*) 0x40380888UL)
#define CYREG_TCPWM0_GRP0_CNT17_CC0     ((volatile un_TCPWM_GRP_CNT_CC0_t*) 0x40380890UL)
#define CYREG_TCPWM0_GRP0_CNT17_CC0_BUFF ((volatile un_TCPWM_GRP_CNT_CC0_BUFF_t*) 0x40380894UL)
#define CYREG_TCPWM0_GRP0_CNT17_CC1     ((volatile un_TCPWM_GRP_CNT_CC1_t*) 0x40380898UL)
#define CYREG_TCPWM0_GRP0_CNT17_CC1_BUFF ((volatile un_TCPWM_GRP_CNT_CC1_BUFF_t*) 0x4038089CUL)
#define CYREG_TCPWM0_GRP0_CNT17_PERIOD  ((volatile un_TCPWM_GRP_CNT_PERIOD_t*) 0x403808A0UL)
#define CYREG_TCPWM0_GRP0_CNT17_PERIOD_BUFF ((volatile un_TCPWM_GRP_CNT_PERIOD_BUFF_t*) 0x403808A4UL)
#define CYREG_TCPWM0_GRP0_CNT17_DT      ((volatile un_TCPWM_GRP_CNT_DT_t*) 0x403808B0UL)
#define CYREG_TCPWM0_GRP0_CNT17_TR_CMD  ((volatile un_TCPWM_GRP_CNT_TR_CMD_t*) 0x403808C0UL)
#define CYREG_TCPWM0_GRP0_CNT17_TR_IN_SEL0 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL0_t*) 0x403808C4UL)
#define CYREG_TCPWM0_GRP0_CNT17_TR_IN_SEL1 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL1_t*) 0x403808C8UL)
#define CYREG_TCPWM0_GRP0_CNT17_TR_IN_EDGE_SEL ((volatile un_TCPWM_GRP_CNT_TR_IN_EDGE_SEL_t*) 0x403808CCUL)
#define CYREG_TCPWM0_GRP0_CNT17_TR_PWM_CTRL ((volatile un_TCPWM_GRP_CNT_TR_PWM_CTRL_t*) 0x403808D0UL)
#define CYREG_TCPWM0_GRP0_CNT17_TR_OUT_SEL ((volatile un_TCPWM_GRP_CNT_TR_OUT_SEL_t*) 0x403808D4UL)
#define CYREG_TCPWM0_GRP0_CNT17_INTR    ((volatile un_TCPWM_GRP_CNT_INTR_t*) 0x403808F0UL)
#define CYREG_TCPWM0_GRP0_CNT17_INTR_SET ((volatile un_TCPWM_GRP_CNT_INTR_SET_t*) 0x403808F4UL)
#define CYREG_TCPWM0_GRP0_CNT17_INTR_MASK ((volatile un_TCPWM_GRP_CNT_INTR_MASK_t*) 0x403808F8UL)
#define CYREG_TCPWM0_GRP0_CNT17_INTR_MASKED ((volatile un_TCPWM_GRP_CNT_INTR_MASKED_t*) 0x403808FCUL)

/**
  * \brief Timer/Counter/PWM Counter Module (TCPWM_GRP_CNT18)
  */
#define CYREG_TCPWM0_GRP0_CNT18_CTRL    ((volatile un_TCPWM_GRP_CNT_CTRL_t*) 0x40380900UL)
#define CYREG_TCPWM0_GRP0_CNT18_STATUS  ((volatile un_TCPWM_GRP_CNT_STATUS_t*) 0x40380904UL)
#define CYREG_TCPWM0_GRP0_CNT18_COUNTER ((volatile un_TCPWM_GRP_CNT_COUNTER_t*) 0x40380908UL)
#define CYREG_TCPWM0_GRP0_CNT18_CC0     ((volatile un_TCPWM_GRP_CNT_CC0_t*) 0x40380910UL)
#define CYREG_TCPWM0_GRP0_CNT18_CC0_BUFF ((volatile un_TCPWM_GRP_CNT_CC0_BUFF_t*) 0x40380914UL)
#define CYREG_TCPWM0_GRP0_CNT18_CC1     ((volatile un_TCPWM_GRP_CNT_CC1_t*) 0x40380918UL)
#define CYREG_TCPWM0_GRP0_CNT18_CC1_BUFF ((volatile un_TCPWM_GRP_CNT_CC1_BUFF_t*) 0x4038091CUL)
#define CYREG_TCPWM0_GRP0_CNT18_PERIOD  ((volatile un_TCPWM_GRP_CNT_PERIOD_t*) 0x40380920UL)
#define CYREG_TCPWM0_GRP0_CNT18_PERIOD_BUFF ((volatile un_TCPWM_GRP_CNT_PERIOD_BUFF_t*) 0x40380924UL)
#define CYREG_TCPWM0_GRP0_CNT18_DT      ((volatile un_TCPWM_GRP_CNT_DT_t*) 0x40380930UL)
#define CYREG_TCPWM0_GRP0_CNT18_TR_CMD  ((volatile un_TCPWM_GRP_CNT_TR_CMD_t*) 0x40380940UL)
#define CYREG_TCPWM0_GRP0_CNT18_TR_IN_SEL0 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL0_t*) 0x40380944UL)
#define CYREG_TCPWM0_GRP0_CNT18_TR_IN_SEL1 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL1_t*) 0x40380948UL)
#define CYREG_TCPWM0_GRP0_CNT18_TR_IN_EDGE_SEL ((volatile un_TCPWM_GRP_CNT_TR_IN_EDGE_SEL_t*) 0x4038094CUL)
#define CYREG_TCPWM0_GRP0_CNT18_TR_PWM_CTRL ((volatile un_TCPWM_GRP_CNT_TR_PWM_CTRL_t*) 0x40380950UL)
#define CYREG_TCPWM0_GRP0_CNT18_TR_OUT_SEL ((volatile un_TCPWM_GRP_CNT_TR_OUT_SEL_t*) 0x40380954UL)
#define CYREG_TCPWM0_GRP0_CNT18_INTR    ((volatile un_TCPWM_GRP_CNT_INTR_t*) 0x40380970UL)
#define CYREG_TCPWM0_GRP0_CNT18_INTR_SET ((volatile un_TCPWM_GRP_CNT_INTR_SET_t*) 0x40380974UL)
#define CYREG_TCPWM0_GRP0_CNT18_INTR_MASK ((volatile un_TCPWM_GRP_CNT_INTR_MASK_t*) 0x40380978UL)
#define CYREG_TCPWM0_GRP0_CNT18_INTR_MASKED ((volatile un_TCPWM_GRP_CNT_INTR_MASKED_t*) 0x4038097CUL)

/**
  * \brief Timer/Counter/PWM Counter Module (TCPWM_GRP_CNT19)
  */
#define CYREG_TCPWM0_GRP0_CNT19_CTRL    ((volatile un_TCPWM_GRP_CNT_CTRL_t*) 0x40380980UL)
#define CYREG_TCPWM0_GRP0_CNT19_STATUS  ((volatile un_TCPWM_GRP_CNT_STATUS_t*) 0x40380984UL)
#define CYREG_TCPWM0_GRP0_CNT19_COUNTER ((volatile un_TCPWM_GRP_CNT_COUNTER_t*) 0x40380988UL)
#define CYREG_TCPWM0_GRP0_CNT19_CC0     ((volatile un_TCPWM_GRP_CNT_CC0_t*) 0x40380990UL)
#define CYREG_TCPWM0_GRP0_CNT19_CC0_BUFF ((volatile un_TCPWM_GRP_CNT_CC0_BUFF_t*) 0x40380994UL)
#define CYREG_TCPWM0_GRP0_CNT19_CC1     ((volatile un_TCPWM_GRP_CNT_CC1_t*) 0x40380998UL)
#define CYREG_TCPWM0_GRP0_CNT19_CC1_BUFF ((volatile un_TCPWM_GRP_CNT_CC1_BUFF_t*) 0x4038099CUL)
#define CYREG_TCPWM0_GRP0_CNT19_PERIOD  ((volatile un_TCPWM_GRP_CNT_PERIOD_t*) 0x403809A0UL)
#define CYREG_TCPWM0_GRP0_CNT19_PERIOD_BUFF ((volatile un_TCPWM_GRP_CNT_PERIOD_BUFF_t*) 0x403809A4UL)
#define CYREG_TCPWM0_GRP0_CNT19_DT      ((volatile un_TCPWM_GRP_CNT_DT_t*) 0x403809B0UL)
#define CYREG_TCPWM0_GRP0_CNT19_TR_CMD  ((volatile un_TCPWM_GRP_CNT_TR_CMD_t*) 0x403809C0UL)
#define CYREG_TCPWM0_GRP0_CNT19_TR_IN_SEL0 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL0_t*) 0x403809C4UL)
#define CYREG_TCPWM0_GRP0_CNT19_TR_IN_SEL1 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL1_t*) 0x403809C8UL)
#define CYREG_TCPWM0_GRP0_CNT19_TR_IN_EDGE_SEL ((volatile un_TCPWM_GRP_CNT_TR_IN_EDGE_SEL_t*) 0x403809CCUL)
#define CYREG_TCPWM0_GRP0_CNT19_TR_PWM_CTRL ((volatile un_TCPWM_GRP_CNT_TR_PWM_CTRL_t*) 0x403809D0UL)
#define CYREG_TCPWM0_GRP0_CNT19_TR_OUT_SEL ((volatile un_TCPWM_GRP_CNT_TR_OUT_SEL_t*) 0x403809D4UL)
#define CYREG_TCPWM0_GRP0_CNT19_INTR    ((volatile un_TCPWM_GRP_CNT_INTR_t*) 0x403809F0UL)
#define CYREG_TCPWM0_GRP0_CNT19_INTR_SET ((volatile un_TCPWM_GRP_CNT_INTR_SET_t*) 0x403809F4UL)
#define CYREG_TCPWM0_GRP0_CNT19_INTR_MASK ((volatile un_TCPWM_GRP_CNT_INTR_MASK_t*) 0x403809F8UL)
#define CYREG_TCPWM0_GRP0_CNT19_INTR_MASKED ((volatile un_TCPWM_GRP_CNT_INTR_MASKED_t*) 0x403809FCUL)

/**
  * \brief Timer/Counter/PWM Counter Module (TCPWM_GRP_CNT20)
  */
#define CYREG_TCPWM0_GRP0_CNT20_CTRL    ((volatile un_TCPWM_GRP_CNT_CTRL_t*) 0x40380A00UL)
#define CYREG_TCPWM0_GRP0_CNT20_STATUS  ((volatile un_TCPWM_GRP_CNT_STATUS_t*) 0x40380A04UL)
#define CYREG_TCPWM0_GRP0_CNT20_COUNTER ((volatile un_TCPWM_GRP_CNT_COUNTER_t*) 0x40380A08UL)
#define CYREG_TCPWM0_GRP0_CNT20_CC0     ((volatile un_TCPWM_GRP_CNT_CC0_t*) 0x40380A10UL)
#define CYREG_TCPWM0_GRP0_CNT20_CC0_BUFF ((volatile un_TCPWM_GRP_CNT_CC0_BUFF_t*) 0x40380A14UL)
#define CYREG_TCPWM0_GRP0_CNT20_CC1     ((volatile un_TCPWM_GRP_CNT_CC1_t*) 0x40380A18UL)
#define CYREG_TCPWM0_GRP0_CNT20_CC1_BUFF ((volatile un_TCPWM_GRP_CNT_CC1_BUFF_t*) 0x40380A1CUL)
#define CYREG_TCPWM0_GRP0_CNT20_PERIOD  ((volatile un_TCPWM_GRP_CNT_PERIOD_t*) 0x40380A20UL)
#define CYREG_TCPWM0_GRP0_CNT20_PERIOD_BUFF ((volatile un_TCPWM_GRP_CNT_PERIOD_BUFF_t*) 0x40380A24UL)
#define CYREG_TCPWM0_GRP0_CNT20_DT      ((volatile un_TCPWM_GRP_CNT_DT_t*) 0x40380A30UL)
#define CYREG_TCPWM0_GRP0_CNT20_TR_CMD  ((volatile un_TCPWM_GRP_CNT_TR_CMD_t*) 0x40380A40UL)
#define CYREG_TCPWM0_GRP0_CNT20_TR_IN_SEL0 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL0_t*) 0x40380A44UL)
#define CYREG_TCPWM0_GRP0_CNT20_TR_IN_SEL1 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL1_t*) 0x40380A48UL)
#define CYREG_TCPWM0_GRP0_CNT20_TR_IN_EDGE_SEL ((volatile un_TCPWM_GRP_CNT_TR_IN_EDGE_SEL_t*) 0x40380A4CUL)
#define CYREG_TCPWM0_GRP0_CNT20_TR_PWM_CTRL ((volatile un_TCPWM_GRP_CNT_TR_PWM_CTRL_t*) 0x40380A50UL)
#define CYREG_TCPWM0_GRP0_CNT20_TR_OUT_SEL ((volatile un_TCPWM_GRP_CNT_TR_OUT_SEL_t*) 0x40380A54UL)
#define CYREG_TCPWM0_GRP0_CNT20_INTR    ((volatile un_TCPWM_GRP_CNT_INTR_t*) 0x40380A70UL)
#define CYREG_TCPWM0_GRP0_CNT20_INTR_SET ((volatile un_TCPWM_GRP_CNT_INTR_SET_t*) 0x40380A74UL)
#define CYREG_TCPWM0_GRP0_CNT20_INTR_MASK ((volatile un_TCPWM_GRP_CNT_INTR_MASK_t*) 0x40380A78UL)
#define CYREG_TCPWM0_GRP0_CNT20_INTR_MASKED ((volatile un_TCPWM_GRP_CNT_INTR_MASKED_t*) 0x40380A7CUL)

/**
  * \brief Timer/Counter/PWM Counter Module (TCPWM_GRP_CNT21)
  */
#define CYREG_TCPWM0_GRP0_CNT21_CTRL    ((volatile un_TCPWM_GRP_CNT_CTRL_t*) 0x40380A80UL)
#define CYREG_TCPWM0_GRP0_CNT21_STATUS  ((volatile un_TCPWM_GRP_CNT_STATUS_t*) 0x40380A84UL)
#define CYREG_TCPWM0_GRP0_CNT21_COUNTER ((volatile un_TCPWM_GRP_CNT_COUNTER_t*) 0x40380A88UL)
#define CYREG_TCPWM0_GRP0_CNT21_CC0     ((volatile un_TCPWM_GRP_CNT_CC0_t*) 0x40380A90UL)
#define CYREG_TCPWM0_GRP0_CNT21_CC0_BUFF ((volatile un_TCPWM_GRP_CNT_CC0_BUFF_t*) 0x40380A94UL)
#define CYREG_TCPWM0_GRP0_CNT21_CC1     ((volatile un_TCPWM_GRP_CNT_CC1_t*) 0x40380A98UL)
#define CYREG_TCPWM0_GRP0_CNT21_CC1_BUFF ((volatile un_TCPWM_GRP_CNT_CC1_BUFF_t*) 0x40380A9CUL)
#define CYREG_TCPWM0_GRP0_CNT21_PERIOD  ((volatile un_TCPWM_GRP_CNT_PERIOD_t*) 0x40380AA0UL)
#define CYREG_TCPWM0_GRP0_CNT21_PERIOD_BUFF ((volatile un_TCPWM_GRP_CNT_PERIOD_BUFF_t*) 0x40380AA4UL)
#define CYREG_TCPWM0_GRP0_CNT21_DT      ((volatile un_TCPWM_GRP_CNT_DT_t*) 0x40380AB0UL)
#define CYREG_TCPWM0_GRP0_CNT21_TR_CMD  ((volatile un_TCPWM_GRP_CNT_TR_CMD_t*) 0x40380AC0UL)
#define CYREG_TCPWM0_GRP0_CNT21_TR_IN_SEL0 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL0_t*) 0x40380AC4UL)
#define CYREG_TCPWM0_GRP0_CNT21_TR_IN_SEL1 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL1_t*) 0x40380AC8UL)
#define CYREG_TCPWM0_GRP0_CNT21_TR_IN_EDGE_SEL ((volatile un_TCPWM_GRP_CNT_TR_IN_EDGE_SEL_t*) 0x40380ACCUL)
#define CYREG_TCPWM0_GRP0_CNT21_TR_PWM_CTRL ((volatile un_TCPWM_GRP_CNT_TR_PWM_CTRL_t*) 0x40380AD0UL)
#define CYREG_TCPWM0_GRP0_CNT21_TR_OUT_SEL ((volatile un_TCPWM_GRP_CNT_TR_OUT_SEL_t*) 0x40380AD4UL)
#define CYREG_TCPWM0_GRP0_CNT21_INTR    ((volatile un_TCPWM_GRP_CNT_INTR_t*) 0x40380AF0UL)
#define CYREG_TCPWM0_GRP0_CNT21_INTR_SET ((volatile un_TCPWM_GRP_CNT_INTR_SET_t*) 0x40380AF4UL)
#define CYREG_TCPWM0_GRP0_CNT21_INTR_MASK ((volatile un_TCPWM_GRP_CNT_INTR_MASK_t*) 0x40380AF8UL)
#define CYREG_TCPWM0_GRP0_CNT21_INTR_MASKED ((volatile un_TCPWM_GRP_CNT_INTR_MASKED_t*) 0x40380AFCUL)

/**
  * \brief Timer/Counter/PWM Counter Module (TCPWM_GRP_CNT22)
  */
#define CYREG_TCPWM0_GRP0_CNT22_CTRL    ((volatile un_TCPWM_GRP_CNT_CTRL_t*) 0x40380B00UL)
#define CYREG_TCPWM0_GRP0_CNT22_STATUS  ((volatile un_TCPWM_GRP_CNT_STATUS_t*) 0x40380B04UL)
#define CYREG_TCPWM0_GRP0_CNT22_COUNTER ((volatile un_TCPWM_GRP_CNT_COUNTER_t*) 0x40380B08UL)
#define CYREG_TCPWM0_GRP0_CNT22_CC0     ((volatile un_TCPWM_GRP_CNT_CC0_t*) 0x40380B10UL)
#define CYREG_TCPWM0_GRP0_CNT22_CC0_BUFF ((volatile un_TCPWM_GRP_CNT_CC0_BUFF_t*) 0x40380B14UL)
#define CYREG_TCPWM0_GRP0_CNT22_CC1     ((volatile un_TCPWM_GRP_CNT_CC1_t*) 0x40380B18UL)
#define CYREG_TCPWM0_GRP0_CNT22_CC1_BUFF ((volatile un_TCPWM_GRP_CNT_CC1_BUFF_t*) 0x40380B1CUL)
#define CYREG_TCPWM0_GRP0_CNT22_PERIOD  ((volatile un_TCPWM_GRP_CNT_PERIOD_t*) 0x40380B20UL)
#define CYREG_TCPWM0_GRP0_CNT22_PERIOD_BUFF ((volatile un_TCPWM_GRP_CNT_PERIOD_BUFF_t*) 0x40380B24UL)
#define CYREG_TCPWM0_GRP0_CNT22_DT      ((volatile un_TCPWM_GRP_CNT_DT_t*) 0x40380B30UL)
#define CYREG_TCPWM0_GRP0_CNT22_TR_CMD  ((volatile un_TCPWM_GRP_CNT_TR_CMD_t*) 0x40380B40UL)
#define CYREG_TCPWM0_GRP0_CNT22_TR_IN_SEL0 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL0_t*) 0x40380B44UL)
#define CYREG_TCPWM0_GRP0_CNT22_TR_IN_SEL1 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL1_t*) 0x40380B48UL)
#define CYREG_TCPWM0_GRP0_CNT22_TR_IN_EDGE_SEL ((volatile un_TCPWM_GRP_CNT_TR_IN_EDGE_SEL_t*) 0x40380B4CUL)
#define CYREG_TCPWM0_GRP0_CNT22_TR_PWM_CTRL ((volatile un_TCPWM_GRP_CNT_TR_PWM_CTRL_t*) 0x40380B50UL)
#define CYREG_TCPWM0_GRP0_CNT22_TR_OUT_SEL ((volatile un_TCPWM_GRP_CNT_TR_OUT_SEL_t*) 0x40380B54UL)
#define CYREG_TCPWM0_GRP0_CNT22_INTR    ((volatile un_TCPWM_GRP_CNT_INTR_t*) 0x40380B70UL)
#define CYREG_TCPWM0_GRP0_CNT22_INTR_SET ((volatile un_TCPWM_GRP_CNT_INTR_SET_t*) 0x40380B74UL)
#define CYREG_TCPWM0_GRP0_CNT22_INTR_MASK ((volatile un_TCPWM_GRP_CNT_INTR_MASK_t*) 0x40380B78UL)
#define CYREG_TCPWM0_GRP0_CNT22_INTR_MASKED ((volatile un_TCPWM_GRP_CNT_INTR_MASKED_t*) 0x40380B7CUL)

/**
  * \brief Timer/Counter/PWM Counter Module (TCPWM_GRP_CNT23)
  */
#define CYREG_TCPWM0_GRP0_CNT23_CTRL    ((volatile un_TCPWM_GRP_CNT_CTRL_t*) 0x40380B80UL)
#define CYREG_TCPWM0_GRP0_CNT23_STATUS  ((volatile un_TCPWM_GRP_CNT_STATUS_t*) 0x40380B84UL)
#define CYREG_TCPWM0_GRP0_CNT23_COUNTER ((volatile un_TCPWM_GRP_CNT_COUNTER_t*) 0x40380B88UL)
#define CYREG_TCPWM0_GRP0_CNT23_CC0     ((volatile un_TCPWM_GRP_CNT_CC0_t*) 0x40380B90UL)
#define CYREG_TCPWM0_GRP0_CNT23_CC0_BUFF ((volatile un_TCPWM_GRP_CNT_CC0_BUFF_t*) 0x40380B94UL)
#define CYREG_TCPWM0_GRP0_CNT23_CC1     ((volatile un_TCPWM_GRP_CNT_CC1_t*) 0x40380B98UL)
#define CYREG_TCPWM0_GRP0_CNT23_CC1_BUFF ((volatile un_TCPWM_GRP_CNT_CC1_BUFF_t*) 0x40380B9CUL)
#define CYREG_TCPWM0_GRP0_CNT23_PERIOD  ((volatile un_TCPWM_GRP_CNT_PERIOD_t*) 0x40380BA0UL)
#define CYREG_TCPWM0_GRP0_CNT23_PERIOD_BUFF ((volatile un_TCPWM_GRP_CNT_PERIOD_BUFF_t*) 0x40380BA4UL)
#define CYREG_TCPWM0_GRP0_CNT23_DT      ((volatile un_TCPWM_GRP_CNT_DT_t*) 0x40380BB0UL)
#define CYREG_TCPWM0_GRP0_CNT23_TR_CMD  ((volatile un_TCPWM_GRP_CNT_TR_CMD_t*) 0x40380BC0UL)
#define CYREG_TCPWM0_GRP0_CNT23_TR_IN_SEL0 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL0_t*) 0x40380BC4UL)
#define CYREG_TCPWM0_GRP0_CNT23_TR_IN_SEL1 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL1_t*) 0x40380BC8UL)
#define CYREG_TCPWM0_GRP0_CNT23_TR_IN_EDGE_SEL ((volatile un_TCPWM_GRP_CNT_TR_IN_EDGE_SEL_t*) 0x40380BCCUL)
#define CYREG_TCPWM0_GRP0_CNT23_TR_PWM_CTRL ((volatile un_TCPWM_GRP_CNT_TR_PWM_CTRL_t*) 0x40380BD0UL)
#define CYREG_TCPWM0_GRP0_CNT23_TR_OUT_SEL ((volatile un_TCPWM_GRP_CNT_TR_OUT_SEL_t*) 0x40380BD4UL)
#define CYREG_TCPWM0_GRP0_CNT23_INTR    ((volatile un_TCPWM_GRP_CNT_INTR_t*) 0x40380BF0UL)
#define CYREG_TCPWM0_GRP0_CNT23_INTR_SET ((volatile un_TCPWM_GRP_CNT_INTR_SET_t*) 0x40380BF4UL)
#define CYREG_TCPWM0_GRP0_CNT23_INTR_MASK ((volatile un_TCPWM_GRP_CNT_INTR_MASK_t*) 0x40380BF8UL)
#define CYREG_TCPWM0_GRP0_CNT23_INTR_MASKED ((volatile un_TCPWM_GRP_CNT_INTR_MASKED_t*) 0x40380BFCUL)

/**
  * \brief Timer/Counter/PWM Counter Module (TCPWM_GRP_CNT24)
  */
#define CYREG_TCPWM0_GRP0_CNT24_CTRL    ((volatile un_TCPWM_GRP_CNT_CTRL_t*) 0x40380C00UL)
#define CYREG_TCPWM0_GRP0_CNT24_STATUS  ((volatile un_TCPWM_GRP_CNT_STATUS_t*) 0x40380C04UL)
#define CYREG_TCPWM0_GRP0_CNT24_COUNTER ((volatile un_TCPWM_GRP_CNT_COUNTER_t*) 0x40380C08UL)
#define CYREG_TCPWM0_GRP0_CNT24_CC0     ((volatile un_TCPWM_GRP_CNT_CC0_t*) 0x40380C10UL)
#define CYREG_TCPWM0_GRP0_CNT24_CC0_BUFF ((volatile un_TCPWM_GRP_CNT_CC0_BUFF_t*) 0x40380C14UL)
#define CYREG_TCPWM0_GRP0_CNT24_CC1     ((volatile un_TCPWM_GRP_CNT_CC1_t*) 0x40380C18UL)
#define CYREG_TCPWM0_GRP0_CNT24_CC1_BUFF ((volatile un_TCPWM_GRP_CNT_CC1_BUFF_t*) 0x40380C1CUL)
#define CYREG_TCPWM0_GRP0_CNT24_PERIOD  ((volatile un_TCPWM_GRP_CNT_PERIOD_t*) 0x40380C20UL)
#define CYREG_TCPWM0_GRP0_CNT24_PERIOD_BUFF ((volatile un_TCPWM_GRP_CNT_PERIOD_BUFF_t*) 0x40380C24UL)
#define CYREG_TCPWM0_GRP0_CNT24_DT      ((volatile un_TCPWM_GRP_CNT_DT_t*) 0x40380C30UL)
#define CYREG_TCPWM0_GRP0_CNT24_TR_CMD  ((volatile un_TCPWM_GRP_CNT_TR_CMD_t*) 0x40380C40UL)
#define CYREG_TCPWM0_GRP0_CNT24_TR_IN_SEL0 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL0_t*) 0x40380C44UL)
#define CYREG_TCPWM0_GRP0_CNT24_TR_IN_SEL1 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL1_t*) 0x40380C48UL)
#define CYREG_TCPWM0_GRP0_CNT24_TR_IN_EDGE_SEL ((volatile un_TCPWM_GRP_CNT_TR_IN_EDGE_SEL_t*) 0x40380C4CUL)
#define CYREG_TCPWM0_GRP0_CNT24_TR_PWM_CTRL ((volatile un_TCPWM_GRP_CNT_TR_PWM_CTRL_t*) 0x40380C50UL)
#define CYREG_TCPWM0_GRP0_CNT24_TR_OUT_SEL ((volatile un_TCPWM_GRP_CNT_TR_OUT_SEL_t*) 0x40380C54UL)
#define CYREG_TCPWM0_GRP0_CNT24_INTR    ((volatile un_TCPWM_GRP_CNT_INTR_t*) 0x40380C70UL)
#define CYREG_TCPWM0_GRP0_CNT24_INTR_SET ((volatile un_TCPWM_GRP_CNT_INTR_SET_t*) 0x40380C74UL)
#define CYREG_TCPWM0_GRP0_CNT24_INTR_MASK ((volatile un_TCPWM_GRP_CNT_INTR_MASK_t*) 0x40380C78UL)
#define CYREG_TCPWM0_GRP0_CNT24_INTR_MASKED ((volatile un_TCPWM_GRP_CNT_INTR_MASKED_t*) 0x40380C7CUL)

/**
  * \brief Timer/Counter/PWM Counter Module (TCPWM_GRP_CNT25)
  */
#define CYREG_TCPWM0_GRP0_CNT25_CTRL    ((volatile un_TCPWM_GRP_CNT_CTRL_t*) 0x40380C80UL)
#define CYREG_TCPWM0_GRP0_CNT25_STATUS  ((volatile un_TCPWM_GRP_CNT_STATUS_t*) 0x40380C84UL)
#define CYREG_TCPWM0_GRP0_CNT25_COUNTER ((volatile un_TCPWM_GRP_CNT_COUNTER_t*) 0x40380C88UL)
#define CYREG_TCPWM0_GRP0_CNT25_CC0     ((volatile un_TCPWM_GRP_CNT_CC0_t*) 0x40380C90UL)
#define CYREG_TCPWM0_GRP0_CNT25_CC0_BUFF ((volatile un_TCPWM_GRP_CNT_CC0_BUFF_t*) 0x40380C94UL)
#define CYREG_TCPWM0_GRP0_CNT25_CC1     ((volatile un_TCPWM_GRP_CNT_CC1_t*) 0x40380C98UL)
#define CYREG_TCPWM0_GRP0_CNT25_CC1_BUFF ((volatile un_TCPWM_GRP_CNT_CC1_BUFF_t*) 0x40380C9CUL)
#define CYREG_TCPWM0_GRP0_CNT25_PERIOD  ((volatile un_TCPWM_GRP_CNT_PERIOD_t*) 0x40380CA0UL)
#define CYREG_TCPWM0_GRP0_CNT25_PERIOD_BUFF ((volatile un_TCPWM_GRP_CNT_PERIOD_BUFF_t*) 0x40380CA4UL)
#define CYREG_TCPWM0_GRP0_CNT25_DT      ((volatile un_TCPWM_GRP_CNT_DT_t*) 0x40380CB0UL)
#define CYREG_TCPWM0_GRP0_CNT25_TR_CMD  ((volatile un_TCPWM_GRP_CNT_TR_CMD_t*) 0x40380CC0UL)
#define CYREG_TCPWM0_GRP0_CNT25_TR_IN_SEL0 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL0_t*) 0x40380CC4UL)
#define CYREG_TCPWM0_GRP0_CNT25_TR_IN_SEL1 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL1_t*) 0x40380CC8UL)
#define CYREG_TCPWM0_GRP0_CNT25_TR_IN_EDGE_SEL ((volatile un_TCPWM_GRP_CNT_TR_IN_EDGE_SEL_t*) 0x40380CCCUL)
#define CYREG_TCPWM0_GRP0_CNT25_TR_PWM_CTRL ((volatile un_TCPWM_GRP_CNT_TR_PWM_CTRL_t*) 0x40380CD0UL)
#define CYREG_TCPWM0_GRP0_CNT25_TR_OUT_SEL ((volatile un_TCPWM_GRP_CNT_TR_OUT_SEL_t*) 0x40380CD4UL)
#define CYREG_TCPWM0_GRP0_CNT25_INTR    ((volatile un_TCPWM_GRP_CNT_INTR_t*) 0x40380CF0UL)
#define CYREG_TCPWM0_GRP0_CNT25_INTR_SET ((volatile un_TCPWM_GRP_CNT_INTR_SET_t*) 0x40380CF4UL)
#define CYREG_TCPWM0_GRP0_CNT25_INTR_MASK ((volatile un_TCPWM_GRP_CNT_INTR_MASK_t*) 0x40380CF8UL)
#define CYREG_TCPWM0_GRP0_CNT25_INTR_MASKED ((volatile un_TCPWM_GRP_CNT_INTR_MASKED_t*) 0x40380CFCUL)

/**
  * \brief Timer/Counter/PWM Counter Module (TCPWM_GRP_CNT26)
  */
#define CYREG_TCPWM0_GRP0_CNT26_CTRL    ((volatile un_TCPWM_GRP_CNT_CTRL_t*) 0x40380D00UL)
#define CYREG_TCPWM0_GRP0_CNT26_STATUS  ((volatile un_TCPWM_GRP_CNT_STATUS_t*) 0x40380D04UL)
#define CYREG_TCPWM0_GRP0_CNT26_COUNTER ((volatile un_TCPWM_GRP_CNT_COUNTER_t*) 0x40380D08UL)
#define CYREG_TCPWM0_GRP0_CNT26_CC0     ((volatile un_TCPWM_GRP_CNT_CC0_t*) 0x40380D10UL)
#define CYREG_TCPWM0_GRP0_CNT26_CC0_BUFF ((volatile un_TCPWM_GRP_CNT_CC0_BUFF_t*) 0x40380D14UL)
#define CYREG_TCPWM0_GRP0_CNT26_CC1     ((volatile un_TCPWM_GRP_CNT_CC1_t*) 0x40380D18UL)
#define CYREG_TCPWM0_GRP0_CNT26_CC1_BUFF ((volatile un_TCPWM_GRP_CNT_CC1_BUFF_t*) 0x40380D1CUL)
#define CYREG_TCPWM0_GRP0_CNT26_PERIOD  ((volatile un_TCPWM_GRP_CNT_PERIOD_t*) 0x40380D20UL)
#define CYREG_TCPWM0_GRP0_CNT26_PERIOD_BUFF ((volatile un_TCPWM_GRP_CNT_PERIOD_BUFF_t*) 0x40380D24UL)
#define CYREG_TCPWM0_GRP0_CNT26_DT      ((volatile un_TCPWM_GRP_CNT_DT_t*) 0x40380D30UL)
#define CYREG_TCPWM0_GRP0_CNT26_TR_CMD  ((volatile un_TCPWM_GRP_CNT_TR_CMD_t*) 0x40380D40UL)
#define CYREG_TCPWM0_GRP0_CNT26_TR_IN_SEL0 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL0_t*) 0x40380D44UL)
#define CYREG_TCPWM0_GRP0_CNT26_TR_IN_SEL1 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL1_t*) 0x40380D48UL)
#define CYREG_TCPWM0_GRP0_CNT26_TR_IN_EDGE_SEL ((volatile un_TCPWM_GRP_CNT_TR_IN_EDGE_SEL_t*) 0x40380D4CUL)
#define CYREG_TCPWM0_GRP0_CNT26_TR_PWM_CTRL ((volatile un_TCPWM_GRP_CNT_TR_PWM_CTRL_t*) 0x40380D50UL)
#define CYREG_TCPWM0_GRP0_CNT26_TR_OUT_SEL ((volatile un_TCPWM_GRP_CNT_TR_OUT_SEL_t*) 0x40380D54UL)
#define CYREG_TCPWM0_GRP0_CNT26_INTR    ((volatile un_TCPWM_GRP_CNT_INTR_t*) 0x40380D70UL)
#define CYREG_TCPWM0_GRP0_CNT26_INTR_SET ((volatile un_TCPWM_GRP_CNT_INTR_SET_t*) 0x40380D74UL)
#define CYREG_TCPWM0_GRP0_CNT26_INTR_MASK ((volatile un_TCPWM_GRP_CNT_INTR_MASK_t*) 0x40380D78UL)
#define CYREG_TCPWM0_GRP0_CNT26_INTR_MASKED ((volatile un_TCPWM_GRP_CNT_INTR_MASKED_t*) 0x40380D7CUL)

/**
  * \brief Timer/Counter/PWM Counter Module (TCPWM_GRP_CNT27)
  */
#define CYREG_TCPWM0_GRP0_CNT27_CTRL    ((volatile un_TCPWM_GRP_CNT_CTRL_t*) 0x40380D80UL)
#define CYREG_TCPWM0_GRP0_CNT27_STATUS  ((volatile un_TCPWM_GRP_CNT_STATUS_t*) 0x40380D84UL)
#define CYREG_TCPWM0_GRP0_CNT27_COUNTER ((volatile un_TCPWM_GRP_CNT_COUNTER_t*) 0x40380D88UL)
#define CYREG_TCPWM0_GRP0_CNT27_CC0     ((volatile un_TCPWM_GRP_CNT_CC0_t*) 0x40380D90UL)
#define CYREG_TCPWM0_GRP0_CNT27_CC0_BUFF ((volatile un_TCPWM_GRP_CNT_CC0_BUFF_t*) 0x40380D94UL)
#define CYREG_TCPWM0_GRP0_CNT27_CC1     ((volatile un_TCPWM_GRP_CNT_CC1_t*) 0x40380D98UL)
#define CYREG_TCPWM0_GRP0_CNT27_CC1_BUFF ((volatile un_TCPWM_GRP_CNT_CC1_BUFF_t*) 0x40380D9CUL)
#define CYREG_TCPWM0_GRP0_CNT27_PERIOD  ((volatile un_TCPWM_GRP_CNT_PERIOD_t*) 0x40380DA0UL)
#define CYREG_TCPWM0_GRP0_CNT27_PERIOD_BUFF ((volatile un_TCPWM_GRP_CNT_PERIOD_BUFF_t*) 0x40380DA4UL)
#define CYREG_TCPWM0_GRP0_CNT27_DT      ((volatile un_TCPWM_GRP_CNT_DT_t*) 0x40380DB0UL)
#define CYREG_TCPWM0_GRP0_CNT27_TR_CMD  ((volatile un_TCPWM_GRP_CNT_TR_CMD_t*) 0x40380DC0UL)
#define CYREG_TCPWM0_GRP0_CNT27_TR_IN_SEL0 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL0_t*) 0x40380DC4UL)
#define CYREG_TCPWM0_GRP0_CNT27_TR_IN_SEL1 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL1_t*) 0x40380DC8UL)
#define CYREG_TCPWM0_GRP0_CNT27_TR_IN_EDGE_SEL ((volatile un_TCPWM_GRP_CNT_TR_IN_EDGE_SEL_t*) 0x40380DCCUL)
#define CYREG_TCPWM0_GRP0_CNT27_TR_PWM_CTRL ((volatile un_TCPWM_GRP_CNT_TR_PWM_CTRL_t*) 0x40380DD0UL)
#define CYREG_TCPWM0_GRP0_CNT27_TR_OUT_SEL ((volatile un_TCPWM_GRP_CNT_TR_OUT_SEL_t*) 0x40380DD4UL)
#define CYREG_TCPWM0_GRP0_CNT27_INTR    ((volatile un_TCPWM_GRP_CNT_INTR_t*) 0x40380DF0UL)
#define CYREG_TCPWM0_GRP0_CNT27_INTR_SET ((volatile un_TCPWM_GRP_CNT_INTR_SET_t*) 0x40380DF4UL)
#define CYREG_TCPWM0_GRP0_CNT27_INTR_MASK ((volatile un_TCPWM_GRP_CNT_INTR_MASK_t*) 0x40380DF8UL)
#define CYREG_TCPWM0_GRP0_CNT27_INTR_MASKED ((volatile un_TCPWM_GRP_CNT_INTR_MASKED_t*) 0x40380DFCUL)

/**
  * \brief Timer/Counter/PWM Counter Module (TCPWM_GRP_CNT28)
  */
#define CYREG_TCPWM0_GRP0_CNT28_CTRL    ((volatile un_TCPWM_GRP_CNT_CTRL_t*) 0x40380E00UL)
#define CYREG_TCPWM0_GRP0_CNT28_STATUS  ((volatile un_TCPWM_GRP_CNT_STATUS_t*) 0x40380E04UL)
#define CYREG_TCPWM0_GRP0_CNT28_COUNTER ((volatile un_TCPWM_GRP_CNT_COUNTER_t*) 0x40380E08UL)
#define CYREG_TCPWM0_GRP0_CNT28_CC0     ((volatile un_TCPWM_GRP_CNT_CC0_t*) 0x40380E10UL)
#define CYREG_TCPWM0_GRP0_CNT28_CC0_BUFF ((volatile un_TCPWM_GRP_CNT_CC0_BUFF_t*) 0x40380E14UL)
#define CYREG_TCPWM0_GRP0_CNT28_CC1     ((volatile un_TCPWM_GRP_CNT_CC1_t*) 0x40380E18UL)
#define CYREG_TCPWM0_GRP0_CNT28_CC1_BUFF ((volatile un_TCPWM_GRP_CNT_CC1_BUFF_t*) 0x40380E1CUL)
#define CYREG_TCPWM0_GRP0_CNT28_PERIOD  ((volatile un_TCPWM_GRP_CNT_PERIOD_t*) 0x40380E20UL)
#define CYREG_TCPWM0_GRP0_CNT28_PERIOD_BUFF ((volatile un_TCPWM_GRP_CNT_PERIOD_BUFF_t*) 0x40380E24UL)
#define CYREG_TCPWM0_GRP0_CNT28_DT      ((volatile un_TCPWM_GRP_CNT_DT_t*) 0x40380E30UL)
#define CYREG_TCPWM0_GRP0_CNT28_TR_CMD  ((volatile un_TCPWM_GRP_CNT_TR_CMD_t*) 0x40380E40UL)
#define CYREG_TCPWM0_GRP0_CNT28_TR_IN_SEL0 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL0_t*) 0x40380E44UL)
#define CYREG_TCPWM0_GRP0_CNT28_TR_IN_SEL1 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL1_t*) 0x40380E48UL)
#define CYREG_TCPWM0_GRP0_CNT28_TR_IN_EDGE_SEL ((volatile un_TCPWM_GRP_CNT_TR_IN_EDGE_SEL_t*) 0x40380E4CUL)
#define CYREG_TCPWM0_GRP0_CNT28_TR_PWM_CTRL ((volatile un_TCPWM_GRP_CNT_TR_PWM_CTRL_t*) 0x40380E50UL)
#define CYREG_TCPWM0_GRP0_CNT28_TR_OUT_SEL ((volatile un_TCPWM_GRP_CNT_TR_OUT_SEL_t*) 0x40380E54UL)
#define CYREG_TCPWM0_GRP0_CNT28_INTR    ((volatile un_TCPWM_GRP_CNT_INTR_t*) 0x40380E70UL)
#define CYREG_TCPWM0_GRP0_CNT28_INTR_SET ((volatile un_TCPWM_GRP_CNT_INTR_SET_t*) 0x40380E74UL)
#define CYREG_TCPWM0_GRP0_CNT28_INTR_MASK ((volatile un_TCPWM_GRP_CNT_INTR_MASK_t*) 0x40380E78UL)
#define CYREG_TCPWM0_GRP0_CNT28_INTR_MASKED ((volatile un_TCPWM_GRP_CNT_INTR_MASKED_t*) 0x40380E7CUL)

/**
  * \brief Timer/Counter/PWM Counter Module (TCPWM_GRP_CNT29)
  */
#define CYREG_TCPWM0_GRP0_CNT29_CTRL    ((volatile un_TCPWM_GRP_CNT_CTRL_t*) 0x40380E80UL)
#define CYREG_TCPWM0_GRP0_CNT29_STATUS  ((volatile un_TCPWM_GRP_CNT_STATUS_t*) 0x40380E84UL)
#define CYREG_TCPWM0_GRP0_CNT29_COUNTER ((volatile un_TCPWM_GRP_CNT_COUNTER_t*) 0x40380E88UL)
#define CYREG_TCPWM0_GRP0_CNT29_CC0     ((volatile un_TCPWM_GRP_CNT_CC0_t*) 0x40380E90UL)
#define CYREG_TCPWM0_GRP0_CNT29_CC0_BUFF ((volatile un_TCPWM_GRP_CNT_CC0_BUFF_t*) 0x40380E94UL)
#define CYREG_TCPWM0_GRP0_CNT29_CC1     ((volatile un_TCPWM_GRP_CNT_CC1_t*) 0x40380E98UL)
#define CYREG_TCPWM0_GRP0_CNT29_CC1_BUFF ((volatile un_TCPWM_GRP_CNT_CC1_BUFF_t*) 0x40380E9CUL)
#define CYREG_TCPWM0_GRP0_CNT29_PERIOD  ((volatile un_TCPWM_GRP_CNT_PERIOD_t*) 0x40380EA0UL)
#define CYREG_TCPWM0_GRP0_CNT29_PERIOD_BUFF ((volatile un_TCPWM_GRP_CNT_PERIOD_BUFF_t*) 0x40380EA4UL)
#define CYREG_TCPWM0_GRP0_CNT29_DT      ((volatile un_TCPWM_GRP_CNT_DT_t*) 0x40380EB0UL)
#define CYREG_TCPWM0_GRP0_CNT29_TR_CMD  ((volatile un_TCPWM_GRP_CNT_TR_CMD_t*) 0x40380EC0UL)
#define CYREG_TCPWM0_GRP0_CNT29_TR_IN_SEL0 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL0_t*) 0x40380EC4UL)
#define CYREG_TCPWM0_GRP0_CNT29_TR_IN_SEL1 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL1_t*) 0x40380EC8UL)
#define CYREG_TCPWM0_GRP0_CNT29_TR_IN_EDGE_SEL ((volatile un_TCPWM_GRP_CNT_TR_IN_EDGE_SEL_t*) 0x40380ECCUL)
#define CYREG_TCPWM0_GRP0_CNT29_TR_PWM_CTRL ((volatile un_TCPWM_GRP_CNT_TR_PWM_CTRL_t*) 0x40380ED0UL)
#define CYREG_TCPWM0_GRP0_CNT29_TR_OUT_SEL ((volatile un_TCPWM_GRP_CNT_TR_OUT_SEL_t*) 0x40380ED4UL)
#define CYREG_TCPWM0_GRP0_CNT29_INTR    ((volatile un_TCPWM_GRP_CNT_INTR_t*) 0x40380EF0UL)
#define CYREG_TCPWM0_GRP0_CNT29_INTR_SET ((volatile un_TCPWM_GRP_CNT_INTR_SET_t*) 0x40380EF4UL)
#define CYREG_TCPWM0_GRP0_CNT29_INTR_MASK ((volatile un_TCPWM_GRP_CNT_INTR_MASK_t*) 0x40380EF8UL)
#define CYREG_TCPWM0_GRP0_CNT29_INTR_MASKED ((volatile un_TCPWM_GRP_CNT_INTR_MASKED_t*) 0x40380EFCUL)

/**
  * \brief Timer/Counter/PWM Counter Module (TCPWM_GRP_CNT30)
  */
#define CYREG_TCPWM0_GRP0_CNT30_CTRL    ((volatile un_TCPWM_GRP_CNT_CTRL_t*) 0x40380F00UL)
#define CYREG_TCPWM0_GRP0_CNT30_STATUS  ((volatile un_TCPWM_GRP_CNT_STATUS_t*) 0x40380F04UL)
#define CYREG_TCPWM0_GRP0_CNT30_COUNTER ((volatile un_TCPWM_GRP_CNT_COUNTER_t*) 0x40380F08UL)
#define CYREG_TCPWM0_GRP0_CNT30_CC0     ((volatile un_TCPWM_GRP_CNT_CC0_t*) 0x40380F10UL)
#define CYREG_TCPWM0_GRP0_CNT30_CC0_BUFF ((volatile un_TCPWM_GRP_CNT_CC0_BUFF_t*) 0x40380F14UL)
#define CYREG_TCPWM0_GRP0_CNT30_CC1     ((volatile un_TCPWM_GRP_CNT_CC1_t*) 0x40380F18UL)
#define CYREG_TCPWM0_GRP0_CNT30_CC1_BUFF ((volatile un_TCPWM_GRP_CNT_CC1_BUFF_t*) 0x40380F1CUL)
#define CYREG_TCPWM0_GRP0_CNT30_PERIOD  ((volatile un_TCPWM_GRP_CNT_PERIOD_t*) 0x40380F20UL)
#define CYREG_TCPWM0_GRP0_CNT30_PERIOD_BUFF ((volatile un_TCPWM_GRP_CNT_PERIOD_BUFF_t*) 0x40380F24UL)
#define CYREG_TCPWM0_GRP0_CNT30_DT      ((volatile un_TCPWM_GRP_CNT_DT_t*) 0x40380F30UL)
#define CYREG_TCPWM0_GRP0_CNT30_TR_CMD  ((volatile un_TCPWM_GRP_CNT_TR_CMD_t*) 0x40380F40UL)
#define CYREG_TCPWM0_GRP0_CNT30_TR_IN_SEL0 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL0_t*) 0x40380F44UL)
#define CYREG_TCPWM0_GRP0_CNT30_TR_IN_SEL1 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL1_t*) 0x40380F48UL)
#define CYREG_TCPWM0_GRP0_CNT30_TR_IN_EDGE_SEL ((volatile un_TCPWM_GRP_CNT_TR_IN_EDGE_SEL_t*) 0x40380F4CUL)
#define CYREG_TCPWM0_GRP0_CNT30_TR_PWM_CTRL ((volatile un_TCPWM_GRP_CNT_TR_PWM_CTRL_t*) 0x40380F50UL)
#define CYREG_TCPWM0_GRP0_CNT30_TR_OUT_SEL ((volatile un_TCPWM_GRP_CNT_TR_OUT_SEL_t*) 0x40380F54UL)
#define CYREG_TCPWM0_GRP0_CNT30_INTR    ((volatile un_TCPWM_GRP_CNT_INTR_t*) 0x40380F70UL)
#define CYREG_TCPWM0_GRP0_CNT30_INTR_SET ((volatile un_TCPWM_GRP_CNT_INTR_SET_t*) 0x40380F74UL)
#define CYREG_TCPWM0_GRP0_CNT30_INTR_MASK ((volatile un_TCPWM_GRP_CNT_INTR_MASK_t*) 0x40380F78UL)
#define CYREG_TCPWM0_GRP0_CNT30_INTR_MASKED ((volatile un_TCPWM_GRP_CNT_INTR_MASKED_t*) 0x40380F7CUL)

/**
  * \brief Timer/Counter/PWM Counter Module (TCPWM_GRP_CNT31)
  */
#define CYREG_TCPWM0_GRP0_CNT31_CTRL    ((volatile un_TCPWM_GRP_CNT_CTRL_t*) 0x40380F80UL)
#define CYREG_TCPWM0_GRP0_CNT31_STATUS  ((volatile un_TCPWM_GRP_CNT_STATUS_t*) 0x40380F84UL)
#define CYREG_TCPWM0_GRP0_CNT31_COUNTER ((volatile un_TCPWM_GRP_CNT_COUNTER_t*) 0x40380F88UL)
#define CYREG_TCPWM0_GRP0_CNT31_CC0     ((volatile un_TCPWM_GRP_CNT_CC0_t*) 0x40380F90UL)
#define CYREG_TCPWM0_GRP0_CNT31_CC0_BUFF ((volatile un_TCPWM_GRP_CNT_CC0_BUFF_t*) 0x40380F94UL)
#define CYREG_TCPWM0_GRP0_CNT31_CC1     ((volatile un_TCPWM_GRP_CNT_CC1_t*) 0x40380F98UL)
#define CYREG_TCPWM0_GRP0_CNT31_CC1_BUFF ((volatile un_TCPWM_GRP_CNT_CC1_BUFF_t*) 0x40380F9CUL)
#define CYREG_TCPWM0_GRP0_CNT31_PERIOD  ((volatile un_TCPWM_GRP_CNT_PERIOD_t*) 0x40380FA0UL)
#define CYREG_TCPWM0_GRP0_CNT31_PERIOD_BUFF ((volatile un_TCPWM_GRP_CNT_PERIOD_BUFF_t*) 0x40380FA4UL)
#define CYREG_TCPWM0_GRP0_CNT31_DT      ((volatile un_TCPWM_GRP_CNT_DT_t*) 0x40380FB0UL)
#define CYREG_TCPWM0_GRP0_CNT31_TR_CMD  ((volatile un_TCPWM_GRP_CNT_TR_CMD_t*) 0x40380FC0UL)
#define CYREG_TCPWM0_GRP0_CNT31_TR_IN_SEL0 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL0_t*) 0x40380FC4UL)
#define CYREG_TCPWM0_GRP0_CNT31_TR_IN_SEL1 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL1_t*) 0x40380FC8UL)
#define CYREG_TCPWM0_GRP0_CNT31_TR_IN_EDGE_SEL ((volatile un_TCPWM_GRP_CNT_TR_IN_EDGE_SEL_t*) 0x40380FCCUL)
#define CYREG_TCPWM0_GRP0_CNT31_TR_PWM_CTRL ((volatile un_TCPWM_GRP_CNT_TR_PWM_CTRL_t*) 0x40380FD0UL)
#define CYREG_TCPWM0_GRP0_CNT31_TR_OUT_SEL ((volatile un_TCPWM_GRP_CNT_TR_OUT_SEL_t*) 0x40380FD4UL)
#define CYREG_TCPWM0_GRP0_CNT31_INTR    ((volatile un_TCPWM_GRP_CNT_INTR_t*) 0x40380FF0UL)
#define CYREG_TCPWM0_GRP0_CNT31_INTR_SET ((volatile un_TCPWM_GRP_CNT_INTR_SET_t*) 0x40380FF4UL)
#define CYREG_TCPWM0_GRP0_CNT31_INTR_MASK ((volatile un_TCPWM_GRP_CNT_INTR_MASK_t*) 0x40380FF8UL)
#define CYREG_TCPWM0_GRP0_CNT31_INTR_MASKED ((volatile un_TCPWM_GRP_CNT_INTR_MASKED_t*) 0x40380FFCUL)

/**
  * \brief Timer/Counter/PWM Counter Module (TCPWM_GRP_CNT32)
  */
#define CYREG_TCPWM0_GRP0_CNT32_CTRL    ((volatile un_TCPWM_GRP_CNT_CTRL_t*) 0x40381000UL)
#define CYREG_TCPWM0_GRP0_CNT32_STATUS  ((volatile un_TCPWM_GRP_CNT_STATUS_t*) 0x40381004UL)
#define CYREG_TCPWM0_GRP0_CNT32_COUNTER ((volatile un_TCPWM_GRP_CNT_COUNTER_t*) 0x40381008UL)
#define CYREG_TCPWM0_GRP0_CNT32_CC0     ((volatile un_TCPWM_GRP_CNT_CC0_t*) 0x40381010UL)
#define CYREG_TCPWM0_GRP0_CNT32_CC0_BUFF ((volatile un_TCPWM_GRP_CNT_CC0_BUFF_t*) 0x40381014UL)
#define CYREG_TCPWM0_GRP0_CNT32_CC1     ((volatile un_TCPWM_GRP_CNT_CC1_t*) 0x40381018UL)
#define CYREG_TCPWM0_GRP0_CNT32_CC1_BUFF ((volatile un_TCPWM_GRP_CNT_CC1_BUFF_t*) 0x4038101CUL)
#define CYREG_TCPWM0_GRP0_CNT32_PERIOD  ((volatile un_TCPWM_GRP_CNT_PERIOD_t*) 0x40381020UL)
#define CYREG_TCPWM0_GRP0_CNT32_PERIOD_BUFF ((volatile un_TCPWM_GRP_CNT_PERIOD_BUFF_t*) 0x40381024UL)
#define CYREG_TCPWM0_GRP0_CNT32_DT      ((volatile un_TCPWM_GRP_CNT_DT_t*) 0x40381030UL)
#define CYREG_TCPWM0_GRP0_CNT32_TR_CMD  ((volatile un_TCPWM_GRP_CNT_TR_CMD_t*) 0x40381040UL)
#define CYREG_TCPWM0_GRP0_CNT32_TR_IN_SEL0 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL0_t*) 0x40381044UL)
#define CYREG_TCPWM0_GRP0_CNT32_TR_IN_SEL1 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL1_t*) 0x40381048UL)
#define CYREG_TCPWM0_GRP0_CNT32_TR_IN_EDGE_SEL ((volatile un_TCPWM_GRP_CNT_TR_IN_EDGE_SEL_t*) 0x4038104CUL)
#define CYREG_TCPWM0_GRP0_CNT32_TR_PWM_CTRL ((volatile un_TCPWM_GRP_CNT_TR_PWM_CTRL_t*) 0x40381050UL)
#define CYREG_TCPWM0_GRP0_CNT32_TR_OUT_SEL ((volatile un_TCPWM_GRP_CNT_TR_OUT_SEL_t*) 0x40381054UL)
#define CYREG_TCPWM0_GRP0_CNT32_INTR    ((volatile un_TCPWM_GRP_CNT_INTR_t*) 0x40381070UL)
#define CYREG_TCPWM0_GRP0_CNT32_INTR_SET ((volatile un_TCPWM_GRP_CNT_INTR_SET_t*) 0x40381074UL)
#define CYREG_TCPWM0_GRP0_CNT32_INTR_MASK ((volatile un_TCPWM_GRP_CNT_INTR_MASK_t*) 0x40381078UL)
#define CYREG_TCPWM0_GRP0_CNT32_INTR_MASKED ((volatile un_TCPWM_GRP_CNT_INTR_MASKED_t*) 0x4038107CUL)

/**
  * \brief Timer/Counter/PWM Counter Module (TCPWM_GRP_CNT33)
  */
#define CYREG_TCPWM0_GRP0_CNT33_CTRL    ((volatile un_TCPWM_GRP_CNT_CTRL_t*) 0x40381080UL)
#define CYREG_TCPWM0_GRP0_CNT33_STATUS  ((volatile un_TCPWM_GRP_CNT_STATUS_t*) 0x40381084UL)
#define CYREG_TCPWM0_GRP0_CNT33_COUNTER ((volatile un_TCPWM_GRP_CNT_COUNTER_t*) 0x40381088UL)
#define CYREG_TCPWM0_GRP0_CNT33_CC0     ((volatile un_TCPWM_GRP_CNT_CC0_t*) 0x40381090UL)
#define CYREG_TCPWM0_GRP0_CNT33_CC0_BUFF ((volatile un_TCPWM_GRP_CNT_CC0_BUFF_t*) 0x40381094UL)
#define CYREG_TCPWM0_GRP0_CNT33_CC1     ((volatile un_TCPWM_GRP_CNT_CC1_t*) 0x40381098UL)
#define CYREG_TCPWM0_GRP0_CNT33_CC1_BUFF ((volatile un_TCPWM_GRP_CNT_CC1_BUFF_t*) 0x4038109CUL)
#define CYREG_TCPWM0_GRP0_CNT33_PERIOD  ((volatile un_TCPWM_GRP_CNT_PERIOD_t*) 0x403810A0UL)
#define CYREG_TCPWM0_GRP0_CNT33_PERIOD_BUFF ((volatile un_TCPWM_GRP_CNT_PERIOD_BUFF_t*) 0x403810A4UL)
#define CYREG_TCPWM0_GRP0_CNT33_DT      ((volatile un_TCPWM_GRP_CNT_DT_t*) 0x403810B0UL)
#define CYREG_TCPWM0_GRP0_CNT33_TR_CMD  ((volatile un_TCPWM_GRP_CNT_TR_CMD_t*) 0x403810C0UL)
#define CYREG_TCPWM0_GRP0_CNT33_TR_IN_SEL0 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL0_t*) 0x403810C4UL)
#define CYREG_TCPWM0_GRP0_CNT33_TR_IN_SEL1 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL1_t*) 0x403810C8UL)
#define CYREG_TCPWM0_GRP0_CNT33_TR_IN_EDGE_SEL ((volatile un_TCPWM_GRP_CNT_TR_IN_EDGE_SEL_t*) 0x403810CCUL)
#define CYREG_TCPWM0_GRP0_CNT33_TR_PWM_CTRL ((volatile un_TCPWM_GRP_CNT_TR_PWM_CTRL_t*) 0x403810D0UL)
#define CYREG_TCPWM0_GRP0_CNT33_TR_OUT_SEL ((volatile un_TCPWM_GRP_CNT_TR_OUT_SEL_t*) 0x403810D4UL)
#define CYREG_TCPWM0_GRP0_CNT33_INTR    ((volatile un_TCPWM_GRP_CNT_INTR_t*) 0x403810F0UL)
#define CYREG_TCPWM0_GRP0_CNT33_INTR_SET ((volatile un_TCPWM_GRP_CNT_INTR_SET_t*) 0x403810F4UL)
#define CYREG_TCPWM0_GRP0_CNT33_INTR_MASK ((volatile un_TCPWM_GRP_CNT_INTR_MASK_t*) 0x403810F8UL)
#define CYREG_TCPWM0_GRP0_CNT33_INTR_MASKED ((volatile un_TCPWM_GRP_CNT_INTR_MASKED_t*) 0x403810FCUL)

/**
  * \brief Timer/Counter/PWM Counter Module (TCPWM_GRP_CNT34)
  */
#define CYREG_TCPWM0_GRP0_CNT34_CTRL    ((volatile un_TCPWM_GRP_CNT_CTRL_t*) 0x40381100UL)
#define CYREG_TCPWM0_GRP0_CNT34_STATUS  ((volatile un_TCPWM_GRP_CNT_STATUS_t*) 0x40381104UL)
#define CYREG_TCPWM0_GRP0_CNT34_COUNTER ((volatile un_TCPWM_GRP_CNT_COUNTER_t*) 0x40381108UL)
#define CYREG_TCPWM0_GRP0_CNT34_CC0     ((volatile un_TCPWM_GRP_CNT_CC0_t*) 0x40381110UL)
#define CYREG_TCPWM0_GRP0_CNT34_CC0_BUFF ((volatile un_TCPWM_GRP_CNT_CC0_BUFF_t*) 0x40381114UL)
#define CYREG_TCPWM0_GRP0_CNT34_CC1     ((volatile un_TCPWM_GRP_CNT_CC1_t*) 0x40381118UL)
#define CYREG_TCPWM0_GRP0_CNT34_CC1_BUFF ((volatile un_TCPWM_GRP_CNT_CC1_BUFF_t*) 0x4038111CUL)
#define CYREG_TCPWM0_GRP0_CNT34_PERIOD  ((volatile un_TCPWM_GRP_CNT_PERIOD_t*) 0x40381120UL)
#define CYREG_TCPWM0_GRP0_CNT34_PERIOD_BUFF ((volatile un_TCPWM_GRP_CNT_PERIOD_BUFF_t*) 0x40381124UL)
#define CYREG_TCPWM0_GRP0_CNT34_DT      ((volatile un_TCPWM_GRP_CNT_DT_t*) 0x40381130UL)
#define CYREG_TCPWM0_GRP0_CNT34_TR_CMD  ((volatile un_TCPWM_GRP_CNT_TR_CMD_t*) 0x40381140UL)
#define CYREG_TCPWM0_GRP0_CNT34_TR_IN_SEL0 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL0_t*) 0x40381144UL)
#define CYREG_TCPWM0_GRP0_CNT34_TR_IN_SEL1 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL1_t*) 0x40381148UL)
#define CYREG_TCPWM0_GRP0_CNT34_TR_IN_EDGE_SEL ((volatile un_TCPWM_GRP_CNT_TR_IN_EDGE_SEL_t*) 0x4038114CUL)
#define CYREG_TCPWM0_GRP0_CNT34_TR_PWM_CTRL ((volatile un_TCPWM_GRP_CNT_TR_PWM_CTRL_t*) 0x40381150UL)
#define CYREG_TCPWM0_GRP0_CNT34_TR_OUT_SEL ((volatile un_TCPWM_GRP_CNT_TR_OUT_SEL_t*) 0x40381154UL)
#define CYREG_TCPWM0_GRP0_CNT34_INTR    ((volatile un_TCPWM_GRP_CNT_INTR_t*) 0x40381170UL)
#define CYREG_TCPWM0_GRP0_CNT34_INTR_SET ((volatile un_TCPWM_GRP_CNT_INTR_SET_t*) 0x40381174UL)
#define CYREG_TCPWM0_GRP0_CNT34_INTR_MASK ((volatile un_TCPWM_GRP_CNT_INTR_MASK_t*) 0x40381178UL)
#define CYREG_TCPWM0_GRP0_CNT34_INTR_MASKED ((volatile un_TCPWM_GRP_CNT_INTR_MASKED_t*) 0x4038117CUL)

/**
  * \brief Timer/Counter/PWM Counter Module (TCPWM_GRP_CNT35)
  */
#define CYREG_TCPWM0_GRP0_CNT35_CTRL    ((volatile un_TCPWM_GRP_CNT_CTRL_t*) 0x40381180UL)
#define CYREG_TCPWM0_GRP0_CNT35_STATUS  ((volatile un_TCPWM_GRP_CNT_STATUS_t*) 0x40381184UL)
#define CYREG_TCPWM0_GRP0_CNT35_COUNTER ((volatile un_TCPWM_GRP_CNT_COUNTER_t*) 0x40381188UL)
#define CYREG_TCPWM0_GRP0_CNT35_CC0     ((volatile un_TCPWM_GRP_CNT_CC0_t*) 0x40381190UL)
#define CYREG_TCPWM0_GRP0_CNT35_CC0_BUFF ((volatile un_TCPWM_GRP_CNT_CC0_BUFF_t*) 0x40381194UL)
#define CYREG_TCPWM0_GRP0_CNT35_CC1     ((volatile un_TCPWM_GRP_CNT_CC1_t*) 0x40381198UL)
#define CYREG_TCPWM0_GRP0_CNT35_CC1_BUFF ((volatile un_TCPWM_GRP_CNT_CC1_BUFF_t*) 0x4038119CUL)
#define CYREG_TCPWM0_GRP0_CNT35_PERIOD  ((volatile un_TCPWM_GRP_CNT_PERIOD_t*) 0x403811A0UL)
#define CYREG_TCPWM0_GRP0_CNT35_PERIOD_BUFF ((volatile un_TCPWM_GRP_CNT_PERIOD_BUFF_t*) 0x403811A4UL)
#define CYREG_TCPWM0_GRP0_CNT35_DT      ((volatile un_TCPWM_GRP_CNT_DT_t*) 0x403811B0UL)
#define CYREG_TCPWM0_GRP0_CNT35_TR_CMD  ((volatile un_TCPWM_GRP_CNT_TR_CMD_t*) 0x403811C0UL)
#define CYREG_TCPWM0_GRP0_CNT35_TR_IN_SEL0 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL0_t*) 0x403811C4UL)
#define CYREG_TCPWM0_GRP0_CNT35_TR_IN_SEL1 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL1_t*) 0x403811C8UL)
#define CYREG_TCPWM0_GRP0_CNT35_TR_IN_EDGE_SEL ((volatile un_TCPWM_GRP_CNT_TR_IN_EDGE_SEL_t*) 0x403811CCUL)
#define CYREG_TCPWM0_GRP0_CNT35_TR_PWM_CTRL ((volatile un_TCPWM_GRP_CNT_TR_PWM_CTRL_t*) 0x403811D0UL)
#define CYREG_TCPWM0_GRP0_CNT35_TR_OUT_SEL ((volatile un_TCPWM_GRP_CNT_TR_OUT_SEL_t*) 0x403811D4UL)
#define CYREG_TCPWM0_GRP0_CNT35_INTR    ((volatile un_TCPWM_GRP_CNT_INTR_t*) 0x403811F0UL)
#define CYREG_TCPWM0_GRP0_CNT35_INTR_SET ((volatile un_TCPWM_GRP_CNT_INTR_SET_t*) 0x403811F4UL)
#define CYREG_TCPWM0_GRP0_CNT35_INTR_MASK ((volatile un_TCPWM_GRP_CNT_INTR_MASK_t*) 0x403811F8UL)
#define CYREG_TCPWM0_GRP0_CNT35_INTR_MASKED ((volatile un_TCPWM_GRP_CNT_INTR_MASKED_t*) 0x403811FCUL)

/**
  * \brief Timer/Counter/PWM Counter Module (TCPWM_GRP_CNT36)
  */
#define CYREG_TCPWM0_GRP0_CNT36_CTRL    ((volatile un_TCPWM_GRP_CNT_CTRL_t*) 0x40381200UL)
#define CYREG_TCPWM0_GRP0_CNT36_STATUS  ((volatile un_TCPWM_GRP_CNT_STATUS_t*) 0x40381204UL)
#define CYREG_TCPWM0_GRP0_CNT36_COUNTER ((volatile un_TCPWM_GRP_CNT_COUNTER_t*) 0x40381208UL)
#define CYREG_TCPWM0_GRP0_CNT36_CC0     ((volatile un_TCPWM_GRP_CNT_CC0_t*) 0x40381210UL)
#define CYREG_TCPWM0_GRP0_CNT36_CC0_BUFF ((volatile un_TCPWM_GRP_CNT_CC0_BUFF_t*) 0x40381214UL)
#define CYREG_TCPWM0_GRP0_CNT36_CC1     ((volatile un_TCPWM_GRP_CNT_CC1_t*) 0x40381218UL)
#define CYREG_TCPWM0_GRP0_CNT36_CC1_BUFF ((volatile un_TCPWM_GRP_CNT_CC1_BUFF_t*) 0x4038121CUL)
#define CYREG_TCPWM0_GRP0_CNT36_PERIOD  ((volatile un_TCPWM_GRP_CNT_PERIOD_t*) 0x40381220UL)
#define CYREG_TCPWM0_GRP0_CNT36_PERIOD_BUFF ((volatile un_TCPWM_GRP_CNT_PERIOD_BUFF_t*) 0x40381224UL)
#define CYREG_TCPWM0_GRP0_CNT36_DT      ((volatile un_TCPWM_GRP_CNT_DT_t*) 0x40381230UL)
#define CYREG_TCPWM0_GRP0_CNT36_TR_CMD  ((volatile un_TCPWM_GRP_CNT_TR_CMD_t*) 0x40381240UL)
#define CYREG_TCPWM0_GRP0_CNT36_TR_IN_SEL0 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL0_t*) 0x40381244UL)
#define CYREG_TCPWM0_GRP0_CNT36_TR_IN_SEL1 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL1_t*) 0x40381248UL)
#define CYREG_TCPWM0_GRP0_CNT36_TR_IN_EDGE_SEL ((volatile un_TCPWM_GRP_CNT_TR_IN_EDGE_SEL_t*) 0x4038124CUL)
#define CYREG_TCPWM0_GRP0_CNT36_TR_PWM_CTRL ((volatile un_TCPWM_GRP_CNT_TR_PWM_CTRL_t*) 0x40381250UL)
#define CYREG_TCPWM0_GRP0_CNT36_TR_OUT_SEL ((volatile un_TCPWM_GRP_CNT_TR_OUT_SEL_t*) 0x40381254UL)
#define CYREG_TCPWM0_GRP0_CNT36_INTR    ((volatile un_TCPWM_GRP_CNT_INTR_t*) 0x40381270UL)
#define CYREG_TCPWM0_GRP0_CNT36_INTR_SET ((volatile un_TCPWM_GRP_CNT_INTR_SET_t*) 0x40381274UL)
#define CYREG_TCPWM0_GRP0_CNT36_INTR_MASK ((volatile un_TCPWM_GRP_CNT_INTR_MASK_t*) 0x40381278UL)
#define CYREG_TCPWM0_GRP0_CNT36_INTR_MASKED ((volatile un_TCPWM_GRP_CNT_INTR_MASKED_t*) 0x4038127CUL)

/**
  * \brief Timer/Counter/PWM Counter Module (TCPWM_GRP_CNT37)
  */
#define CYREG_TCPWM0_GRP0_CNT37_CTRL    ((volatile un_TCPWM_GRP_CNT_CTRL_t*) 0x40381280UL)
#define CYREG_TCPWM0_GRP0_CNT37_STATUS  ((volatile un_TCPWM_GRP_CNT_STATUS_t*) 0x40381284UL)
#define CYREG_TCPWM0_GRP0_CNT37_COUNTER ((volatile un_TCPWM_GRP_CNT_COUNTER_t*) 0x40381288UL)
#define CYREG_TCPWM0_GRP0_CNT37_CC0     ((volatile un_TCPWM_GRP_CNT_CC0_t*) 0x40381290UL)
#define CYREG_TCPWM0_GRP0_CNT37_CC0_BUFF ((volatile un_TCPWM_GRP_CNT_CC0_BUFF_t*) 0x40381294UL)
#define CYREG_TCPWM0_GRP0_CNT37_CC1     ((volatile un_TCPWM_GRP_CNT_CC1_t*) 0x40381298UL)
#define CYREG_TCPWM0_GRP0_CNT37_CC1_BUFF ((volatile un_TCPWM_GRP_CNT_CC1_BUFF_t*) 0x4038129CUL)
#define CYREG_TCPWM0_GRP0_CNT37_PERIOD  ((volatile un_TCPWM_GRP_CNT_PERIOD_t*) 0x403812A0UL)
#define CYREG_TCPWM0_GRP0_CNT37_PERIOD_BUFF ((volatile un_TCPWM_GRP_CNT_PERIOD_BUFF_t*) 0x403812A4UL)
#define CYREG_TCPWM0_GRP0_CNT37_DT      ((volatile un_TCPWM_GRP_CNT_DT_t*) 0x403812B0UL)
#define CYREG_TCPWM0_GRP0_CNT37_TR_CMD  ((volatile un_TCPWM_GRP_CNT_TR_CMD_t*) 0x403812C0UL)
#define CYREG_TCPWM0_GRP0_CNT37_TR_IN_SEL0 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL0_t*) 0x403812C4UL)
#define CYREG_TCPWM0_GRP0_CNT37_TR_IN_SEL1 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL1_t*) 0x403812C8UL)
#define CYREG_TCPWM0_GRP0_CNT37_TR_IN_EDGE_SEL ((volatile un_TCPWM_GRP_CNT_TR_IN_EDGE_SEL_t*) 0x403812CCUL)
#define CYREG_TCPWM0_GRP0_CNT37_TR_PWM_CTRL ((volatile un_TCPWM_GRP_CNT_TR_PWM_CTRL_t*) 0x403812D0UL)
#define CYREG_TCPWM0_GRP0_CNT37_TR_OUT_SEL ((volatile un_TCPWM_GRP_CNT_TR_OUT_SEL_t*) 0x403812D4UL)
#define CYREG_TCPWM0_GRP0_CNT37_INTR    ((volatile un_TCPWM_GRP_CNT_INTR_t*) 0x403812F0UL)
#define CYREG_TCPWM0_GRP0_CNT37_INTR_SET ((volatile un_TCPWM_GRP_CNT_INTR_SET_t*) 0x403812F4UL)
#define CYREG_TCPWM0_GRP0_CNT37_INTR_MASK ((volatile un_TCPWM_GRP_CNT_INTR_MASK_t*) 0x403812F8UL)
#define CYREG_TCPWM0_GRP0_CNT37_INTR_MASKED ((volatile un_TCPWM_GRP_CNT_INTR_MASKED_t*) 0x403812FCUL)

/**
  * \brief Timer/Counter/PWM Counter Module (TCPWM_GRP_CNT38)
  */
#define CYREG_TCPWM0_GRP0_CNT38_CTRL    ((volatile un_TCPWM_GRP_CNT_CTRL_t*) 0x40381300UL)
#define CYREG_TCPWM0_GRP0_CNT38_STATUS  ((volatile un_TCPWM_GRP_CNT_STATUS_t*) 0x40381304UL)
#define CYREG_TCPWM0_GRP0_CNT38_COUNTER ((volatile un_TCPWM_GRP_CNT_COUNTER_t*) 0x40381308UL)
#define CYREG_TCPWM0_GRP0_CNT38_CC0     ((volatile un_TCPWM_GRP_CNT_CC0_t*) 0x40381310UL)
#define CYREG_TCPWM0_GRP0_CNT38_CC0_BUFF ((volatile un_TCPWM_GRP_CNT_CC0_BUFF_t*) 0x40381314UL)
#define CYREG_TCPWM0_GRP0_CNT38_CC1     ((volatile un_TCPWM_GRP_CNT_CC1_t*) 0x40381318UL)
#define CYREG_TCPWM0_GRP0_CNT38_CC1_BUFF ((volatile un_TCPWM_GRP_CNT_CC1_BUFF_t*) 0x4038131CUL)
#define CYREG_TCPWM0_GRP0_CNT38_PERIOD  ((volatile un_TCPWM_GRP_CNT_PERIOD_t*) 0x40381320UL)
#define CYREG_TCPWM0_GRP0_CNT38_PERIOD_BUFF ((volatile un_TCPWM_GRP_CNT_PERIOD_BUFF_t*) 0x40381324UL)
#define CYREG_TCPWM0_GRP0_CNT38_DT      ((volatile un_TCPWM_GRP_CNT_DT_t*) 0x40381330UL)
#define CYREG_TCPWM0_GRP0_CNT38_TR_CMD  ((volatile un_TCPWM_GRP_CNT_TR_CMD_t*) 0x40381340UL)
#define CYREG_TCPWM0_GRP0_CNT38_TR_IN_SEL0 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL0_t*) 0x40381344UL)
#define CYREG_TCPWM0_GRP0_CNT38_TR_IN_SEL1 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL1_t*) 0x40381348UL)
#define CYREG_TCPWM0_GRP0_CNT38_TR_IN_EDGE_SEL ((volatile un_TCPWM_GRP_CNT_TR_IN_EDGE_SEL_t*) 0x4038134CUL)
#define CYREG_TCPWM0_GRP0_CNT38_TR_PWM_CTRL ((volatile un_TCPWM_GRP_CNT_TR_PWM_CTRL_t*) 0x40381350UL)
#define CYREG_TCPWM0_GRP0_CNT38_TR_OUT_SEL ((volatile un_TCPWM_GRP_CNT_TR_OUT_SEL_t*) 0x40381354UL)
#define CYREG_TCPWM0_GRP0_CNT38_INTR    ((volatile un_TCPWM_GRP_CNT_INTR_t*) 0x40381370UL)
#define CYREG_TCPWM0_GRP0_CNT38_INTR_SET ((volatile un_TCPWM_GRP_CNT_INTR_SET_t*) 0x40381374UL)
#define CYREG_TCPWM0_GRP0_CNT38_INTR_MASK ((volatile un_TCPWM_GRP_CNT_INTR_MASK_t*) 0x40381378UL)
#define CYREG_TCPWM0_GRP0_CNT38_INTR_MASKED ((volatile un_TCPWM_GRP_CNT_INTR_MASKED_t*) 0x4038137CUL)

/**
  * \brief Timer/Counter/PWM Counter Module (TCPWM_GRP_CNT39)
  */
#define CYREG_TCPWM0_GRP0_CNT39_CTRL    ((volatile un_TCPWM_GRP_CNT_CTRL_t*) 0x40381380UL)
#define CYREG_TCPWM0_GRP0_CNT39_STATUS  ((volatile un_TCPWM_GRP_CNT_STATUS_t*) 0x40381384UL)
#define CYREG_TCPWM0_GRP0_CNT39_COUNTER ((volatile un_TCPWM_GRP_CNT_COUNTER_t*) 0x40381388UL)
#define CYREG_TCPWM0_GRP0_CNT39_CC0     ((volatile un_TCPWM_GRP_CNT_CC0_t*) 0x40381390UL)
#define CYREG_TCPWM0_GRP0_CNT39_CC0_BUFF ((volatile un_TCPWM_GRP_CNT_CC0_BUFF_t*) 0x40381394UL)
#define CYREG_TCPWM0_GRP0_CNT39_CC1     ((volatile un_TCPWM_GRP_CNT_CC1_t*) 0x40381398UL)
#define CYREG_TCPWM0_GRP0_CNT39_CC1_BUFF ((volatile un_TCPWM_GRP_CNT_CC1_BUFF_t*) 0x4038139CUL)
#define CYREG_TCPWM0_GRP0_CNT39_PERIOD  ((volatile un_TCPWM_GRP_CNT_PERIOD_t*) 0x403813A0UL)
#define CYREG_TCPWM0_GRP0_CNT39_PERIOD_BUFF ((volatile un_TCPWM_GRP_CNT_PERIOD_BUFF_t*) 0x403813A4UL)
#define CYREG_TCPWM0_GRP0_CNT39_DT      ((volatile un_TCPWM_GRP_CNT_DT_t*) 0x403813B0UL)
#define CYREG_TCPWM0_GRP0_CNT39_TR_CMD  ((volatile un_TCPWM_GRP_CNT_TR_CMD_t*) 0x403813C0UL)
#define CYREG_TCPWM0_GRP0_CNT39_TR_IN_SEL0 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL0_t*) 0x403813C4UL)
#define CYREG_TCPWM0_GRP0_CNT39_TR_IN_SEL1 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL1_t*) 0x403813C8UL)
#define CYREG_TCPWM0_GRP0_CNT39_TR_IN_EDGE_SEL ((volatile un_TCPWM_GRP_CNT_TR_IN_EDGE_SEL_t*) 0x403813CCUL)
#define CYREG_TCPWM0_GRP0_CNT39_TR_PWM_CTRL ((volatile un_TCPWM_GRP_CNT_TR_PWM_CTRL_t*) 0x403813D0UL)
#define CYREG_TCPWM0_GRP0_CNT39_TR_OUT_SEL ((volatile un_TCPWM_GRP_CNT_TR_OUT_SEL_t*) 0x403813D4UL)
#define CYREG_TCPWM0_GRP0_CNT39_INTR    ((volatile un_TCPWM_GRP_CNT_INTR_t*) 0x403813F0UL)
#define CYREG_TCPWM0_GRP0_CNT39_INTR_SET ((volatile un_TCPWM_GRP_CNT_INTR_SET_t*) 0x403813F4UL)
#define CYREG_TCPWM0_GRP0_CNT39_INTR_MASK ((volatile un_TCPWM_GRP_CNT_INTR_MASK_t*) 0x403813F8UL)
#define CYREG_TCPWM0_GRP0_CNT39_INTR_MASKED ((volatile un_TCPWM_GRP_CNT_INTR_MASKED_t*) 0x403813FCUL)

/**
  * \brief Timer/Counter/PWM Counter Module (TCPWM_GRP_CNT40)
  */
#define CYREG_TCPWM0_GRP0_CNT40_CTRL    ((volatile un_TCPWM_GRP_CNT_CTRL_t*) 0x40381400UL)
#define CYREG_TCPWM0_GRP0_CNT40_STATUS  ((volatile un_TCPWM_GRP_CNT_STATUS_t*) 0x40381404UL)
#define CYREG_TCPWM0_GRP0_CNT40_COUNTER ((volatile un_TCPWM_GRP_CNT_COUNTER_t*) 0x40381408UL)
#define CYREG_TCPWM0_GRP0_CNT40_CC0     ((volatile un_TCPWM_GRP_CNT_CC0_t*) 0x40381410UL)
#define CYREG_TCPWM0_GRP0_CNT40_CC0_BUFF ((volatile un_TCPWM_GRP_CNT_CC0_BUFF_t*) 0x40381414UL)
#define CYREG_TCPWM0_GRP0_CNT40_CC1     ((volatile un_TCPWM_GRP_CNT_CC1_t*) 0x40381418UL)
#define CYREG_TCPWM0_GRP0_CNT40_CC1_BUFF ((volatile un_TCPWM_GRP_CNT_CC1_BUFF_t*) 0x4038141CUL)
#define CYREG_TCPWM0_GRP0_CNT40_PERIOD  ((volatile un_TCPWM_GRP_CNT_PERIOD_t*) 0x40381420UL)
#define CYREG_TCPWM0_GRP0_CNT40_PERIOD_BUFF ((volatile un_TCPWM_GRP_CNT_PERIOD_BUFF_t*) 0x40381424UL)
#define CYREG_TCPWM0_GRP0_CNT40_DT      ((volatile un_TCPWM_GRP_CNT_DT_t*) 0x40381430UL)
#define CYREG_TCPWM0_GRP0_CNT40_TR_CMD  ((volatile un_TCPWM_GRP_CNT_TR_CMD_t*) 0x40381440UL)
#define CYREG_TCPWM0_GRP0_CNT40_TR_IN_SEL0 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL0_t*) 0x40381444UL)
#define CYREG_TCPWM0_GRP0_CNT40_TR_IN_SEL1 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL1_t*) 0x40381448UL)
#define CYREG_TCPWM0_GRP0_CNT40_TR_IN_EDGE_SEL ((volatile un_TCPWM_GRP_CNT_TR_IN_EDGE_SEL_t*) 0x4038144CUL)
#define CYREG_TCPWM0_GRP0_CNT40_TR_PWM_CTRL ((volatile un_TCPWM_GRP_CNT_TR_PWM_CTRL_t*) 0x40381450UL)
#define CYREG_TCPWM0_GRP0_CNT40_TR_OUT_SEL ((volatile un_TCPWM_GRP_CNT_TR_OUT_SEL_t*) 0x40381454UL)
#define CYREG_TCPWM0_GRP0_CNT40_INTR    ((volatile un_TCPWM_GRP_CNT_INTR_t*) 0x40381470UL)
#define CYREG_TCPWM0_GRP0_CNT40_INTR_SET ((volatile un_TCPWM_GRP_CNT_INTR_SET_t*) 0x40381474UL)
#define CYREG_TCPWM0_GRP0_CNT40_INTR_MASK ((volatile un_TCPWM_GRP_CNT_INTR_MASK_t*) 0x40381478UL)
#define CYREG_TCPWM0_GRP0_CNT40_INTR_MASKED ((volatile un_TCPWM_GRP_CNT_INTR_MASKED_t*) 0x4038147CUL)

/**
  * \brief Timer/Counter/PWM Counter Module (TCPWM_GRP_CNT41)
  */
#define CYREG_TCPWM0_GRP0_CNT41_CTRL    ((volatile un_TCPWM_GRP_CNT_CTRL_t*) 0x40381480UL)
#define CYREG_TCPWM0_GRP0_CNT41_STATUS  ((volatile un_TCPWM_GRP_CNT_STATUS_t*) 0x40381484UL)
#define CYREG_TCPWM0_GRP0_CNT41_COUNTER ((volatile un_TCPWM_GRP_CNT_COUNTER_t*) 0x40381488UL)
#define CYREG_TCPWM0_GRP0_CNT41_CC0     ((volatile un_TCPWM_GRP_CNT_CC0_t*) 0x40381490UL)
#define CYREG_TCPWM0_GRP0_CNT41_CC0_BUFF ((volatile un_TCPWM_GRP_CNT_CC0_BUFF_t*) 0x40381494UL)
#define CYREG_TCPWM0_GRP0_CNT41_CC1     ((volatile un_TCPWM_GRP_CNT_CC1_t*) 0x40381498UL)
#define CYREG_TCPWM0_GRP0_CNT41_CC1_BUFF ((volatile un_TCPWM_GRP_CNT_CC1_BUFF_t*) 0x4038149CUL)
#define CYREG_TCPWM0_GRP0_CNT41_PERIOD  ((volatile un_TCPWM_GRP_CNT_PERIOD_t*) 0x403814A0UL)
#define CYREG_TCPWM0_GRP0_CNT41_PERIOD_BUFF ((volatile un_TCPWM_GRP_CNT_PERIOD_BUFF_t*) 0x403814A4UL)
#define CYREG_TCPWM0_GRP0_CNT41_DT      ((volatile un_TCPWM_GRP_CNT_DT_t*) 0x403814B0UL)
#define CYREG_TCPWM0_GRP0_CNT41_TR_CMD  ((volatile un_TCPWM_GRP_CNT_TR_CMD_t*) 0x403814C0UL)
#define CYREG_TCPWM0_GRP0_CNT41_TR_IN_SEL0 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL0_t*) 0x403814C4UL)
#define CYREG_TCPWM0_GRP0_CNT41_TR_IN_SEL1 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL1_t*) 0x403814C8UL)
#define CYREG_TCPWM0_GRP0_CNT41_TR_IN_EDGE_SEL ((volatile un_TCPWM_GRP_CNT_TR_IN_EDGE_SEL_t*) 0x403814CCUL)
#define CYREG_TCPWM0_GRP0_CNT41_TR_PWM_CTRL ((volatile un_TCPWM_GRP_CNT_TR_PWM_CTRL_t*) 0x403814D0UL)
#define CYREG_TCPWM0_GRP0_CNT41_TR_OUT_SEL ((volatile un_TCPWM_GRP_CNT_TR_OUT_SEL_t*) 0x403814D4UL)
#define CYREG_TCPWM0_GRP0_CNT41_INTR    ((volatile un_TCPWM_GRP_CNT_INTR_t*) 0x403814F0UL)
#define CYREG_TCPWM0_GRP0_CNT41_INTR_SET ((volatile un_TCPWM_GRP_CNT_INTR_SET_t*) 0x403814F4UL)
#define CYREG_TCPWM0_GRP0_CNT41_INTR_MASK ((volatile un_TCPWM_GRP_CNT_INTR_MASK_t*) 0x403814F8UL)
#define CYREG_TCPWM0_GRP0_CNT41_INTR_MASKED ((volatile un_TCPWM_GRP_CNT_INTR_MASKED_t*) 0x403814FCUL)

/**
  * \brief Timer/Counter/PWM Counter Module (TCPWM_GRP_CNT42)
  */
#define CYREG_TCPWM0_GRP0_CNT42_CTRL    ((volatile un_TCPWM_GRP_CNT_CTRL_t*) 0x40381500UL)
#define CYREG_TCPWM0_GRP0_CNT42_STATUS  ((volatile un_TCPWM_GRP_CNT_STATUS_t*) 0x40381504UL)
#define CYREG_TCPWM0_GRP0_CNT42_COUNTER ((volatile un_TCPWM_GRP_CNT_COUNTER_t*) 0x40381508UL)
#define CYREG_TCPWM0_GRP0_CNT42_CC0     ((volatile un_TCPWM_GRP_CNT_CC0_t*) 0x40381510UL)
#define CYREG_TCPWM0_GRP0_CNT42_CC0_BUFF ((volatile un_TCPWM_GRP_CNT_CC0_BUFF_t*) 0x40381514UL)
#define CYREG_TCPWM0_GRP0_CNT42_CC1     ((volatile un_TCPWM_GRP_CNT_CC1_t*) 0x40381518UL)
#define CYREG_TCPWM0_GRP0_CNT42_CC1_BUFF ((volatile un_TCPWM_GRP_CNT_CC1_BUFF_t*) 0x4038151CUL)
#define CYREG_TCPWM0_GRP0_CNT42_PERIOD  ((volatile un_TCPWM_GRP_CNT_PERIOD_t*) 0x40381520UL)
#define CYREG_TCPWM0_GRP0_CNT42_PERIOD_BUFF ((volatile un_TCPWM_GRP_CNT_PERIOD_BUFF_t*) 0x40381524UL)
#define CYREG_TCPWM0_GRP0_CNT42_DT      ((volatile un_TCPWM_GRP_CNT_DT_t*) 0x40381530UL)
#define CYREG_TCPWM0_GRP0_CNT42_TR_CMD  ((volatile un_TCPWM_GRP_CNT_TR_CMD_t*) 0x40381540UL)
#define CYREG_TCPWM0_GRP0_CNT42_TR_IN_SEL0 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL0_t*) 0x40381544UL)
#define CYREG_TCPWM0_GRP0_CNT42_TR_IN_SEL1 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL1_t*) 0x40381548UL)
#define CYREG_TCPWM0_GRP0_CNT42_TR_IN_EDGE_SEL ((volatile un_TCPWM_GRP_CNT_TR_IN_EDGE_SEL_t*) 0x4038154CUL)
#define CYREG_TCPWM0_GRP0_CNT42_TR_PWM_CTRL ((volatile un_TCPWM_GRP_CNT_TR_PWM_CTRL_t*) 0x40381550UL)
#define CYREG_TCPWM0_GRP0_CNT42_TR_OUT_SEL ((volatile un_TCPWM_GRP_CNT_TR_OUT_SEL_t*) 0x40381554UL)
#define CYREG_TCPWM0_GRP0_CNT42_INTR    ((volatile un_TCPWM_GRP_CNT_INTR_t*) 0x40381570UL)
#define CYREG_TCPWM0_GRP0_CNT42_INTR_SET ((volatile un_TCPWM_GRP_CNT_INTR_SET_t*) 0x40381574UL)
#define CYREG_TCPWM0_GRP0_CNT42_INTR_MASK ((volatile un_TCPWM_GRP_CNT_INTR_MASK_t*) 0x40381578UL)
#define CYREG_TCPWM0_GRP0_CNT42_INTR_MASKED ((volatile un_TCPWM_GRP_CNT_INTR_MASKED_t*) 0x4038157CUL)

/**
  * \brief Timer/Counter/PWM Counter Module (TCPWM_GRP_CNT43)
  */
#define CYREG_TCPWM0_GRP0_CNT43_CTRL    ((volatile un_TCPWM_GRP_CNT_CTRL_t*) 0x40381580UL)
#define CYREG_TCPWM0_GRP0_CNT43_STATUS  ((volatile un_TCPWM_GRP_CNT_STATUS_t*) 0x40381584UL)
#define CYREG_TCPWM0_GRP0_CNT43_COUNTER ((volatile un_TCPWM_GRP_CNT_COUNTER_t*) 0x40381588UL)
#define CYREG_TCPWM0_GRP0_CNT43_CC0     ((volatile un_TCPWM_GRP_CNT_CC0_t*) 0x40381590UL)
#define CYREG_TCPWM0_GRP0_CNT43_CC0_BUFF ((volatile un_TCPWM_GRP_CNT_CC0_BUFF_t*) 0x40381594UL)
#define CYREG_TCPWM0_GRP0_CNT43_CC1     ((volatile un_TCPWM_GRP_CNT_CC1_t*) 0x40381598UL)
#define CYREG_TCPWM0_GRP0_CNT43_CC1_BUFF ((volatile un_TCPWM_GRP_CNT_CC1_BUFF_t*) 0x4038159CUL)
#define CYREG_TCPWM0_GRP0_CNT43_PERIOD  ((volatile un_TCPWM_GRP_CNT_PERIOD_t*) 0x403815A0UL)
#define CYREG_TCPWM0_GRP0_CNT43_PERIOD_BUFF ((volatile un_TCPWM_GRP_CNT_PERIOD_BUFF_t*) 0x403815A4UL)
#define CYREG_TCPWM0_GRP0_CNT43_DT      ((volatile un_TCPWM_GRP_CNT_DT_t*) 0x403815B0UL)
#define CYREG_TCPWM0_GRP0_CNT43_TR_CMD  ((volatile un_TCPWM_GRP_CNT_TR_CMD_t*) 0x403815C0UL)
#define CYREG_TCPWM0_GRP0_CNT43_TR_IN_SEL0 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL0_t*) 0x403815C4UL)
#define CYREG_TCPWM0_GRP0_CNT43_TR_IN_SEL1 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL1_t*) 0x403815C8UL)
#define CYREG_TCPWM0_GRP0_CNT43_TR_IN_EDGE_SEL ((volatile un_TCPWM_GRP_CNT_TR_IN_EDGE_SEL_t*) 0x403815CCUL)
#define CYREG_TCPWM0_GRP0_CNT43_TR_PWM_CTRL ((volatile un_TCPWM_GRP_CNT_TR_PWM_CTRL_t*) 0x403815D0UL)
#define CYREG_TCPWM0_GRP0_CNT43_TR_OUT_SEL ((volatile un_TCPWM_GRP_CNT_TR_OUT_SEL_t*) 0x403815D4UL)
#define CYREG_TCPWM0_GRP0_CNT43_INTR    ((volatile un_TCPWM_GRP_CNT_INTR_t*) 0x403815F0UL)
#define CYREG_TCPWM0_GRP0_CNT43_INTR_SET ((volatile un_TCPWM_GRP_CNT_INTR_SET_t*) 0x403815F4UL)
#define CYREG_TCPWM0_GRP0_CNT43_INTR_MASK ((volatile un_TCPWM_GRP_CNT_INTR_MASK_t*) 0x403815F8UL)
#define CYREG_TCPWM0_GRP0_CNT43_INTR_MASKED ((volatile un_TCPWM_GRP_CNT_INTR_MASKED_t*) 0x403815FCUL)

/**
  * \brief Timer/Counter/PWM Counter Module (TCPWM_GRP_CNT44)
  */
#define CYREG_TCPWM0_GRP0_CNT44_CTRL    ((volatile un_TCPWM_GRP_CNT_CTRL_t*) 0x40381600UL)
#define CYREG_TCPWM0_GRP0_CNT44_STATUS  ((volatile un_TCPWM_GRP_CNT_STATUS_t*) 0x40381604UL)
#define CYREG_TCPWM0_GRP0_CNT44_COUNTER ((volatile un_TCPWM_GRP_CNT_COUNTER_t*) 0x40381608UL)
#define CYREG_TCPWM0_GRP0_CNT44_CC0     ((volatile un_TCPWM_GRP_CNT_CC0_t*) 0x40381610UL)
#define CYREG_TCPWM0_GRP0_CNT44_CC0_BUFF ((volatile un_TCPWM_GRP_CNT_CC0_BUFF_t*) 0x40381614UL)
#define CYREG_TCPWM0_GRP0_CNT44_CC1     ((volatile un_TCPWM_GRP_CNT_CC1_t*) 0x40381618UL)
#define CYREG_TCPWM0_GRP0_CNT44_CC1_BUFF ((volatile un_TCPWM_GRP_CNT_CC1_BUFF_t*) 0x4038161CUL)
#define CYREG_TCPWM0_GRP0_CNT44_PERIOD  ((volatile un_TCPWM_GRP_CNT_PERIOD_t*) 0x40381620UL)
#define CYREG_TCPWM0_GRP0_CNT44_PERIOD_BUFF ((volatile un_TCPWM_GRP_CNT_PERIOD_BUFF_t*) 0x40381624UL)
#define CYREG_TCPWM0_GRP0_CNT44_DT      ((volatile un_TCPWM_GRP_CNT_DT_t*) 0x40381630UL)
#define CYREG_TCPWM0_GRP0_CNT44_TR_CMD  ((volatile un_TCPWM_GRP_CNT_TR_CMD_t*) 0x40381640UL)
#define CYREG_TCPWM0_GRP0_CNT44_TR_IN_SEL0 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL0_t*) 0x40381644UL)
#define CYREG_TCPWM0_GRP0_CNT44_TR_IN_SEL1 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL1_t*) 0x40381648UL)
#define CYREG_TCPWM0_GRP0_CNT44_TR_IN_EDGE_SEL ((volatile un_TCPWM_GRP_CNT_TR_IN_EDGE_SEL_t*) 0x4038164CUL)
#define CYREG_TCPWM0_GRP0_CNT44_TR_PWM_CTRL ((volatile un_TCPWM_GRP_CNT_TR_PWM_CTRL_t*) 0x40381650UL)
#define CYREG_TCPWM0_GRP0_CNT44_TR_OUT_SEL ((volatile un_TCPWM_GRP_CNT_TR_OUT_SEL_t*) 0x40381654UL)
#define CYREG_TCPWM0_GRP0_CNT44_INTR    ((volatile un_TCPWM_GRP_CNT_INTR_t*) 0x40381670UL)
#define CYREG_TCPWM0_GRP0_CNT44_INTR_SET ((volatile un_TCPWM_GRP_CNT_INTR_SET_t*) 0x40381674UL)
#define CYREG_TCPWM0_GRP0_CNT44_INTR_MASK ((volatile un_TCPWM_GRP_CNT_INTR_MASK_t*) 0x40381678UL)
#define CYREG_TCPWM0_GRP0_CNT44_INTR_MASKED ((volatile un_TCPWM_GRP_CNT_INTR_MASKED_t*) 0x4038167CUL)

/**
  * \brief Timer/Counter/PWM Counter Module (TCPWM_GRP_CNT45)
  */
#define CYREG_TCPWM0_GRP0_CNT45_CTRL    ((volatile un_TCPWM_GRP_CNT_CTRL_t*) 0x40381680UL)
#define CYREG_TCPWM0_GRP0_CNT45_STATUS  ((volatile un_TCPWM_GRP_CNT_STATUS_t*) 0x40381684UL)
#define CYREG_TCPWM0_GRP0_CNT45_COUNTER ((volatile un_TCPWM_GRP_CNT_COUNTER_t*) 0x40381688UL)
#define CYREG_TCPWM0_GRP0_CNT45_CC0     ((volatile un_TCPWM_GRP_CNT_CC0_t*) 0x40381690UL)
#define CYREG_TCPWM0_GRP0_CNT45_CC0_BUFF ((volatile un_TCPWM_GRP_CNT_CC0_BUFF_t*) 0x40381694UL)
#define CYREG_TCPWM0_GRP0_CNT45_CC1     ((volatile un_TCPWM_GRP_CNT_CC1_t*) 0x40381698UL)
#define CYREG_TCPWM0_GRP0_CNT45_CC1_BUFF ((volatile un_TCPWM_GRP_CNT_CC1_BUFF_t*) 0x4038169CUL)
#define CYREG_TCPWM0_GRP0_CNT45_PERIOD  ((volatile un_TCPWM_GRP_CNT_PERIOD_t*) 0x403816A0UL)
#define CYREG_TCPWM0_GRP0_CNT45_PERIOD_BUFF ((volatile un_TCPWM_GRP_CNT_PERIOD_BUFF_t*) 0x403816A4UL)
#define CYREG_TCPWM0_GRP0_CNT45_DT      ((volatile un_TCPWM_GRP_CNT_DT_t*) 0x403816B0UL)
#define CYREG_TCPWM0_GRP0_CNT45_TR_CMD  ((volatile un_TCPWM_GRP_CNT_TR_CMD_t*) 0x403816C0UL)
#define CYREG_TCPWM0_GRP0_CNT45_TR_IN_SEL0 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL0_t*) 0x403816C4UL)
#define CYREG_TCPWM0_GRP0_CNT45_TR_IN_SEL1 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL1_t*) 0x403816C8UL)
#define CYREG_TCPWM0_GRP0_CNT45_TR_IN_EDGE_SEL ((volatile un_TCPWM_GRP_CNT_TR_IN_EDGE_SEL_t*) 0x403816CCUL)
#define CYREG_TCPWM0_GRP0_CNT45_TR_PWM_CTRL ((volatile un_TCPWM_GRP_CNT_TR_PWM_CTRL_t*) 0x403816D0UL)
#define CYREG_TCPWM0_GRP0_CNT45_TR_OUT_SEL ((volatile un_TCPWM_GRP_CNT_TR_OUT_SEL_t*) 0x403816D4UL)
#define CYREG_TCPWM0_GRP0_CNT45_INTR    ((volatile un_TCPWM_GRP_CNT_INTR_t*) 0x403816F0UL)
#define CYREG_TCPWM0_GRP0_CNT45_INTR_SET ((volatile un_TCPWM_GRP_CNT_INTR_SET_t*) 0x403816F4UL)
#define CYREG_TCPWM0_GRP0_CNT45_INTR_MASK ((volatile un_TCPWM_GRP_CNT_INTR_MASK_t*) 0x403816F8UL)
#define CYREG_TCPWM0_GRP0_CNT45_INTR_MASKED ((volatile un_TCPWM_GRP_CNT_INTR_MASKED_t*) 0x403816FCUL)

/**
  * \brief Timer/Counter/PWM Counter Module (TCPWM_GRP_CNT46)
  */
#define CYREG_TCPWM0_GRP0_CNT46_CTRL    ((volatile un_TCPWM_GRP_CNT_CTRL_t*) 0x40381700UL)
#define CYREG_TCPWM0_GRP0_CNT46_STATUS  ((volatile un_TCPWM_GRP_CNT_STATUS_t*) 0x40381704UL)
#define CYREG_TCPWM0_GRP0_CNT46_COUNTER ((volatile un_TCPWM_GRP_CNT_COUNTER_t*) 0x40381708UL)
#define CYREG_TCPWM0_GRP0_CNT46_CC0     ((volatile un_TCPWM_GRP_CNT_CC0_t*) 0x40381710UL)
#define CYREG_TCPWM0_GRP0_CNT46_CC0_BUFF ((volatile un_TCPWM_GRP_CNT_CC0_BUFF_t*) 0x40381714UL)
#define CYREG_TCPWM0_GRP0_CNT46_CC1     ((volatile un_TCPWM_GRP_CNT_CC1_t*) 0x40381718UL)
#define CYREG_TCPWM0_GRP0_CNT46_CC1_BUFF ((volatile un_TCPWM_GRP_CNT_CC1_BUFF_t*) 0x4038171CUL)
#define CYREG_TCPWM0_GRP0_CNT46_PERIOD  ((volatile un_TCPWM_GRP_CNT_PERIOD_t*) 0x40381720UL)
#define CYREG_TCPWM0_GRP0_CNT46_PERIOD_BUFF ((volatile un_TCPWM_GRP_CNT_PERIOD_BUFF_t*) 0x40381724UL)
#define CYREG_TCPWM0_GRP0_CNT46_DT      ((volatile un_TCPWM_GRP_CNT_DT_t*) 0x40381730UL)
#define CYREG_TCPWM0_GRP0_CNT46_TR_CMD  ((volatile un_TCPWM_GRP_CNT_TR_CMD_t*) 0x40381740UL)
#define CYREG_TCPWM0_GRP0_CNT46_TR_IN_SEL0 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL0_t*) 0x40381744UL)
#define CYREG_TCPWM0_GRP0_CNT46_TR_IN_SEL1 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL1_t*) 0x40381748UL)
#define CYREG_TCPWM0_GRP0_CNT46_TR_IN_EDGE_SEL ((volatile un_TCPWM_GRP_CNT_TR_IN_EDGE_SEL_t*) 0x4038174CUL)
#define CYREG_TCPWM0_GRP0_CNT46_TR_PWM_CTRL ((volatile un_TCPWM_GRP_CNT_TR_PWM_CTRL_t*) 0x40381750UL)
#define CYREG_TCPWM0_GRP0_CNT46_TR_OUT_SEL ((volatile un_TCPWM_GRP_CNT_TR_OUT_SEL_t*) 0x40381754UL)
#define CYREG_TCPWM0_GRP0_CNT46_INTR    ((volatile un_TCPWM_GRP_CNT_INTR_t*) 0x40381770UL)
#define CYREG_TCPWM0_GRP0_CNT46_INTR_SET ((volatile un_TCPWM_GRP_CNT_INTR_SET_t*) 0x40381774UL)
#define CYREG_TCPWM0_GRP0_CNT46_INTR_MASK ((volatile un_TCPWM_GRP_CNT_INTR_MASK_t*) 0x40381778UL)
#define CYREG_TCPWM0_GRP0_CNT46_INTR_MASKED ((volatile un_TCPWM_GRP_CNT_INTR_MASKED_t*) 0x4038177CUL)

/**
  * \brief Timer/Counter/PWM Counter Module (TCPWM_GRP_CNT47)
  */
#define CYREG_TCPWM0_GRP0_CNT47_CTRL    ((volatile un_TCPWM_GRP_CNT_CTRL_t*) 0x40381780UL)
#define CYREG_TCPWM0_GRP0_CNT47_STATUS  ((volatile un_TCPWM_GRP_CNT_STATUS_t*) 0x40381784UL)
#define CYREG_TCPWM0_GRP0_CNT47_COUNTER ((volatile un_TCPWM_GRP_CNT_COUNTER_t*) 0x40381788UL)
#define CYREG_TCPWM0_GRP0_CNT47_CC0     ((volatile un_TCPWM_GRP_CNT_CC0_t*) 0x40381790UL)
#define CYREG_TCPWM0_GRP0_CNT47_CC0_BUFF ((volatile un_TCPWM_GRP_CNT_CC0_BUFF_t*) 0x40381794UL)
#define CYREG_TCPWM0_GRP0_CNT47_CC1     ((volatile un_TCPWM_GRP_CNT_CC1_t*) 0x40381798UL)
#define CYREG_TCPWM0_GRP0_CNT47_CC1_BUFF ((volatile un_TCPWM_GRP_CNT_CC1_BUFF_t*) 0x4038179CUL)
#define CYREG_TCPWM0_GRP0_CNT47_PERIOD  ((volatile un_TCPWM_GRP_CNT_PERIOD_t*) 0x403817A0UL)
#define CYREG_TCPWM0_GRP0_CNT47_PERIOD_BUFF ((volatile un_TCPWM_GRP_CNT_PERIOD_BUFF_t*) 0x403817A4UL)
#define CYREG_TCPWM0_GRP0_CNT47_DT      ((volatile un_TCPWM_GRP_CNT_DT_t*) 0x403817B0UL)
#define CYREG_TCPWM0_GRP0_CNT47_TR_CMD  ((volatile un_TCPWM_GRP_CNT_TR_CMD_t*) 0x403817C0UL)
#define CYREG_TCPWM0_GRP0_CNT47_TR_IN_SEL0 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL0_t*) 0x403817C4UL)
#define CYREG_TCPWM0_GRP0_CNT47_TR_IN_SEL1 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL1_t*) 0x403817C8UL)
#define CYREG_TCPWM0_GRP0_CNT47_TR_IN_EDGE_SEL ((volatile un_TCPWM_GRP_CNT_TR_IN_EDGE_SEL_t*) 0x403817CCUL)
#define CYREG_TCPWM0_GRP0_CNT47_TR_PWM_CTRL ((volatile un_TCPWM_GRP_CNT_TR_PWM_CTRL_t*) 0x403817D0UL)
#define CYREG_TCPWM0_GRP0_CNT47_TR_OUT_SEL ((volatile un_TCPWM_GRP_CNT_TR_OUT_SEL_t*) 0x403817D4UL)
#define CYREG_TCPWM0_GRP0_CNT47_INTR    ((volatile un_TCPWM_GRP_CNT_INTR_t*) 0x403817F0UL)
#define CYREG_TCPWM0_GRP0_CNT47_INTR_SET ((volatile un_TCPWM_GRP_CNT_INTR_SET_t*) 0x403817F4UL)
#define CYREG_TCPWM0_GRP0_CNT47_INTR_MASK ((volatile un_TCPWM_GRP_CNT_INTR_MASK_t*) 0x403817F8UL)
#define CYREG_TCPWM0_GRP0_CNT47_INTR_MASKED ((volatile un_TCPWM_GRP_CNT_INTR_MASKED_t*) 0x403817FCUL)

/**
  * \brief Timer/Counter/PWM Counter Module (TCPWM_GRP_CNT48)
  */
#define CYREG_TCPWM0_GRP0_CNT48_CTRL    ((volatile un_TCPWM_GRP_CNT_CTRL_t*) 0x40381800UL)
#define CYREG_TCPWM0_GRP0_CNT48_STATUS  ((volatile un_TCPWM_GRP_CNT_STATUS_t*) 0x40381804UL)
#define CYREG_TCPWM0_GRP0_CNT48_COUNTER ((volatile un_TCPWM_GRP_CNT_COUNTER_t*) 0x40381808UL)
#define CYREG_TCPWM0_GRP0_CNT48_CC0     ((volatile un_TCPWM_GRP_CNT_CC0_t*) 0x40381810UL)
#define CYREG_TCPWM0_GRP0_CNT48_CC0_BUFF ((volatile un_TCPWM_GRP_CNT_CC0_BUFF_t*) 0x40381814UL)
#define CYREG_TCPWM0_GRP0_CNT48_CC1     ((volatile un_TCPWM_GRP_CNT_CC1_t*) 0x40381818UL)
#define CYREG_TCPWM0_GRP0_CNT48_CC1_BUFF ((volatile un_TCPWM_GRP_CNT_CC1_BUFF_t*) 0x4038181CUL)
#define CYREG_TCPWM0_GRP0_CNT48_PERIOD  ((volatile un_TCPWM_GRP_CNT_PERIOD_t*) 0x40381820UL)
#define CYREG_TCPWM0_GRP0_CNT48_PERIOD_BUFF ((volatile un_TCPWM_GRP_CNT_PERIOD_BUFF_t*) 0x40381824UL)
#define CYREG_TCPWM0_GRP0_CNT48_DT      ((volatile un_TCPWM_GRP_CNT_DT_t*) 0x40381830UL)
#define CYREG_TCPWM0_GRP0_CNT48_TR_CMD  ((volatile un_TCPWM_GRP_CNT_TR_CMD_t*) 0x40381840UL)
#define CYREG_TCPWM0_GRP0_CNT48_TR_IN_SEL0 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL0_t*) 0x40381844UL)
#define CYREG_TCPWM0_GRP0_CNT48_TR_IN_SEL1 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL1_t*) 0x40381848UL)
#define CYREG_TCPWM0_GRP0_CNT48_TR_IN_EDGE_SEL ((volatile un_TCPWM_GRP_CNT_TR_IN_EDGE_SEL_t*) 0x4038184CUL)
#define CYREG_TCPWM0_GRP0_CNT48_TR_PWM_CTRL ((volatile un_TCPWM_GRP_CNT_TR_PWM_CTRL_t*) 0x40381850UL)
#define CYREG_TCPWM0_GRP0_CNT48_TR_OUT_SEL ((volatile un_TCPWM_GRP_CNT_TR_OUT_SEL_t*) 0x40381854UL)
#define CYREG_TCPWM0_GRP0_CNT48_INTR    ((volatile un_TCPWM_GRP_CNT_INTR_t*) 0x40381870UL)
#define CYREG_TCPWM0_GRP0_CNT48_INTR_SET ((volatile un_TCPWM_GRP_CNT_INTR_SET_t*) 0x40381874UL)
#define CYREG_TCPWM0_GRP0_CNT48_INTR_MASK ((volatile un_TCPWM_GRP_CNT_INTR_MASK_t*) 0x40381878UL)
#define CYREG_TCPWM0_GRP0_CNT48_INTR_MASKED ((volatile un_TCPWM_GRP_CNT_INTR_MASKED_t*) 0x4038187CUL)

/**
  * \brief Timer/Counter/PWM Counter Module (TCPWM_GRP_CNT49)
  */
#define CYREG_TCPWM0_GRP0_CNT49_CTRL    ((volatile un_TCPWM_GRP_CNT_CTRL_t*) 0x40381880UL)
#define CYREG_TCPWM0_GRP0_CNT49_STATUS  ((volatile un_TCPWM_GRP_CNT_STATUS_t*) 0x40381884UL)
#define CYREG_TCPWM0_GRP0_CNT49_COUNTER ((volatile un_TCPWM_GRP_CNT_COUNTER_t*) 0x40381888UL)
#define CYREG_TCPWM0_GRP0_CNT49_CC0     ((volatile un_TCPWM_GRP_CNT_CC0_t*) 0x40381890UL)
#define CYREG_TCPWM0_GRP0_CNT49_CC0_BUFF ((volatile un_TCPWM_GRP_CNT_CC0_BUFF_t*) 0x40381894UL)
#define CYREG_TCPWM0_GRP0_CNT49_CC1     ((volatile un_TCPWM_GRP_CNT_CC1_t*) 0x40381898UL)
#define CYREG_TCPWM0_GRP0_CNT49_CC1_BUFF ((volatile un_TCPWM_GRP_CNT_CC1_BUFF_t*) 0x4038189CUL)
#define CYREG_TCPWM0_GRP0_CNT49_PERIOD  ((volatile un_TCPWM_GRP_CNT_PERIOD_t*) 0x403818A0UL)
#define CYREG_TCPWM0_GRP0_CNT49_PERIOD_BUFF ((volatile un_TCPWM_GRP_CNT_PERIOD_BUFF_t*) 0x403818A4UL)
#define CYREG_TCPWM0_GRP0_CNT49_DT      ((volatile un_TCPWM_GRP_CNT_DT_t*) 0x403818B0UL)
#define CYREG_TCPWM0_GRP0_CNT49_TR_CMD  ((volatile un_TCPWM_GRP_CNT_TR_CMD_t*) 0x403818C0UL)
#define CYREG_TCPWM0_GRP0_CNT49_TR_IN_SEL0 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL0_t*) 0x403818C4UL)
#define CYREG_TCPWM0_GRP0_CNT49_TR_IN_SEL1 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL1_t*) 0x403818C8UL)
#define CYREG_TCPWM0_GRP0_CNT49_TR_IN_EDGE_SEL ((volatile un_TCPWM_GRP_CNT_TR_IN_EDGE_SEL_t*) 0x403818CCUL)
#define CYREG_TCPWM0_GRP0_CNT49_TR_PWM_CTRL ((volatile un_TCPWM_GRP_CNT_TR_PWM_CTRL_t*) 0x403818D0UL)
#define CYREG_TCPWM0_GRP0_CNT49_TR_OUT_SEL ((volatile un_TCPWM_GRP_CNT_TR_OUT_SEL_t*) 0x403818D4UL)
#define CYREG_TCPWM0_GRP0_CNT49_INTR    ((volatile un_TCPWM_GRP_CNT_INTR_t*) 0x403818F0UL)
#define CYREG_TCPWM0_GRP0_CNT49_INTR_SET ((volatile un_TCPWM_GRP_CNT_INTR_SET_t*) 0x403818F4UL)
#define CYREG_TCPWM0_GRP0_CNT49_INTR_MASK ((volatile un_TCPWM_GRP_CNT_INTR_MASK_t*) 0x403818F8UL)
#define CYREG_TCPWM0_GRP0_CNT49_INTR_MASKED ((volatile un_TCPWM_GRP_CNT_INTR_MASKED_t*) 0x403818FCUL)

/**
  * \brief Timer/Counter/PWM Counter Module (TCPWM_GRP_CNT50)
  */
#define CYREG_TCPWM0_GRP0_CNT50_CTRL    ((volatile un_TCPWM_GRP_CNT_CTRL_t*) 0x40381900UL)
#define CYREG_TCPWM0_GRP0_CNT50_STATUS  ((volatile un_TCPWM_GRP_CNT_STATUS_t*) 0x40381904UL)
#define CYREG_TCPWM0_GRP0_CNT50_COUNTER ((volatile un_TCPWM_GRP_CNT_COUNTER_t*) 0x40381908UL)
#define CYREG_TCPWM0_GRP0_CNT50_CC0     ((volatile un_TCPWM_GRP_CNT_CC0_t*) 0x40381910UL)
#define CYREG_TCPWM0_GRP0_CNT50_CC0_BUFF ((volatile un_TCPWM_GRP_CNT_CC0_BUFF_t*) 0x40381914UL)
#define CYREG_TCPWM0_GRP0_CNT50_CC1     ((volatile un_TCPWM_GRP_CNT_CC1_t*) 0x40381918UL)
#define CYREG_TCPWM0_GRP0_CNT50_CC1_BUFF ((volatile un_TCPWM_GRP_CNT_CC1_BUFF_t*) 0x4038191CUL)
#define CYREG_TCPWM0_GRP0_CNT50_PERIOD  ((volatile un_TCPWM_GRP_CNT_PERIOD_t*) 0x40381920UL)
#define CYREG_TCPWM0_GRP0_CNT50_PERIOD_BUFF ((volatile un_TCPWM_GRP_CNT_PERIOD_BUFF_t*) 0x40381924UL)
#define CYREG_TCPWM0_GRP0_CNT50_DT      ((volatile un_TCPWM_GRP_CNT_DT_t*) 0x40381930UL)
#define CYREG_TCPWM0_GRP0_CNT50_TR_CMD  ((volatile un_TCPWM_GRP_CNT_TR_CMD_t*) 0x40381940UL)
#define CYREG_TCPWM0_GRP0_CNT50_TR_IN_SEL0 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL0_t*) 0x40381944UL)
#define CYREG_TCPWM0_GRP0_CNT50_TR_IN_SEL1 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL1_t*) 0x40381948UL)
#define CYREG_TCPWM0_GRP0_CNT50_TR_IN_EDGE_SEL ((volatile un_TCPWM_GRP_CNT_TR_IN_EDGE_SEL_t*) 0x4038194CUL)
#define CYREG_TCPWM0_GRP0_CNT50_TR_PWM_CTRL ((volatile un_TCPWM_GRP_CNT_TR_PWM_CTRL_t*) 0x40381950UL)
#define CYREG_TCPWM0_GRP0_CNT50_TR_OUT_SEL ((volatile un_TCPWM_GRP_CNT_TR_OUT_SEL_t*) 0x40381954UL)
#define CYREG_TCPWM0_GRP0_CNT50_INTR    ((volatile un_TCPWM_GRP_CNT_INTR_t*) 0x40381970UL)
#define CYREG_TCPWM0_GRP0_CNT50_INTR_SET ((volatile un_TCPWM_GRP_CNT_INTR_SET_t*) 0x40381974UL)
#define CYREG_TCPWM0_GRP0_CNT50_INTR_MASK ((volatile un_TCPWM_GRP_CNT_INTR_MASK_t*) 0x40381978UL)
#define CYREG_TCPWM0_GRP0_CNT50_INTR_MASKED ((volatile un_TCPWM_GRP_CNT_INTR_MASKED_t*) 0x4038197CUL)

/**
  * \brief Timer/Counter/PWM Counter Module (TCPWM_GRP_CNT51)
  */
#define CYREG_TCPWM0_GRP0_CNT51_CTRL    ((volatile un_TCPWM_GRP_CNT_CTRL_t*) 0x40381980UL)
#define CYREG_TCPWM0_GRP0_CNT51_STATUS  ((volatile un_TCPWM_GRP_CNT_STATUS_t*) 0x40381984UL)
#define CYREG_TCPWM0_GRP0_CNT51_COUNTER ((volatile un_TCPWM_GRP_CNT_COUNTER_t*) 0x40381988UL)
#define CYREG_TCPWM0_GRP0_CNT51_CC0     ((volatile un_TCPWM_GRP_CNT_CC0_t*) 0x40381990UL)
#define CYREG_TCPWM0_GRP0_CNT51_CC0_BUFF ((volatile un_TCPWM_GRP_CNT_CC0_BUFF_t*) 0x40381994UL)
#define CYREG_TCPWM0_GRP0_CNT51_CC1     ((volatile un_TCPWM_GRP_CNT_CC1_t*) 0x40381998UL)
#define CYREG_TCPWM0_GRP0_CNT51_CC1_BUFF ((volatile un_TCPWM_GRP_CNT_CC1_BUFF_t*) 0x4038199CUL)
#define CYREG_TCPWM0_GRP0_CNT51_PERIOD  ((volatile un_TCPWM_GRP_CNT_PERIOD_t*) 0x403819A0UL)
#define CYREG_TCPWM0_GRP0_CNT51_PERIOD_BUFF ((volatile un_TCPWM_GRP_CNT_PERIOD_BUFF_t*) 0x403819A4UL)
#define CYREG_TCPWM0_GRP0_CNT51_DT      ((volatile un_TCPWM_GRP_CNT_DT_t*) 0x403819B0UL)
#define CYREG_TCPWM0_GRP0_CNT51_TR_CMD  ((volatile un_TCPWM_GRP_CNT_TR_CMD_t*) 0x403819C0UL)
#define CYREG_TCPWM0_GRP0_CNT51_TR_IN_SEL0 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL0_t*) 0x403819C4UL)
#define CYREG_TCPWM0_GRP0_CNT51_TR_IN_SEL1 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL1_t*) 0x403819C8UL)
#define CYREG_TCPWM0_GRP0_CNT51_TR_IN_EDGE_SEL ((volatile un_TCPWM_GRP_CNT_TR_IN_EDGE_SEL_t*) 0x403819CCUL)
#define CYREG_TCPWM0_GRP0_CNT51_TR_PWM_CTRL ((volatile un_TCPWM_GRP_CNT_TR_PWM_CTRL_t*) 0x403819D0UL)
#define CYREG_TCPWM0_GRP0_CNT51_TR_OUT_SEL ((volatile un_TCPWM_GRP_CNT_TR_OUT_SEL_t*) 0x403819D4UL)
#define CYREG_TCPWM0_GRP0_CNT51_INTR    ((volatile un_TCPWM_GRP_CNT_INTR_t*) 0x403819F0UL)
#define CYREG_TCPWM0_GRP0_CNT51_INTR_SET ((volatile un_TCPWM_GRP_CNT_INTR_SET_t*) 0x403819F4UL)
#define CYREG_TCPWM0_GRP0_CNT51_INTR_MASK ((volatile un_TCPWM_GRP_CNT_INTR_MASK_t*) 0x403819F8UL)
#define CYREG_TCPWM0_GRP0_CNT51_INTR_MASKED ((volatile un_TCPWM_GRP_CNT_INTR_MASKED_t*) 0x403819FCUL)

/**
  * \brief Timer/Counter/PWM Counter Module (TCPWM_GRP_CNT52)
  */
#define CYREG_TCPWM0_GRP0_CNT52_CTRL    ((volatile un_TCPWM_GRP_CNT_CTRL_t*) 0x40381A00UL)
#define CYREG_TCPWM0_GRP0_CNT52_STATUS  ((volatile un_TCPWM_GRP_CNT_STATUS_t*) 0x40381A04UL)
#define CYREG_TCPWM0_GRP0_CNT52_COUNTER ((volatile un_TCPWM_GRP_CNT_COUNTER_t*) 0x40381A08UL)
#define CYREG_TCPWM0_GRP0_CNT52_CC0     ((volatile un_TCPWM_GRP_CNT_CC0_t*) 0x40381A10UL)
#define CYREG_TCPWM0_GRP0_CNT52_CC0_BUFF ((volatile un_TCPWM_GRP_CNT_CC0_BUFF_t*) 0x40381A14UL)
#define CYREG_TCPWM0_GRP0_CNT52_CC1     ((volatile un_TCPWM_GRP_CNT_CC1_t*) 0x40381A18UL)
#define CYREG_TCPWM0_GRP0_CNT52_CC1_BUFF ((volatile un_TCPWM_GRP_CNT_CC1_BUFF_t*) 0x40381A1CUL)
#define CYREG_TCPWM0_GRP0_CNT52_PERIOD  ((volatile un_TCPWM_GRP_CNT_PERIOD_t*) 0x40381A20UL)
#define CYREG_TCPWM0_GRP0_CNT52_PERIOD_BUFF ((volatile un_TCPWM_GRP_CNT_PERIOD_BUFF_t*) 0x40381A24UL)
#define CYREG_TCPWM0_GRP0_CNT52_DT      ((volatile un_TCPWM_GRP_CNT_DT_t*) 0x40381A30UL)
#define CYREG_TCPWM0_GRP0_CNT52_TR_CMD  ((volatile un_TCPWM_GRP_CNT_TR_CMD_t*) 0x40381A40UL)
#define CYREG_TCPWM0_GRP0_CNT52_TR_IN_SEL0 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL0_t*) 0x40381A44UL)
#define CYREG_TCPWM0_GRP0_CNT52_TR_IN_SEL1 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL1_t*) 0x40381A48UL)
#define CYREG_TCPWM0_GRP0_CNT52_TR_IN_EDGE_SEL ((volatile un_TCPWM_GRP_CNT_TR_IN_EDGE_SEL_t*) 0x40381A4CUL)
#define CYREG_TCPWM0_GRP0_CNT52_TR_PWM_CTRL ((volatile un_TCPWM_GRP_CNT_TR_PWM_CTRL_t*) 0x40381A50UL)
#define CYREG_TCPWM0_GRP0_CNT52_TR_OUT_SEL ((volatile un_TCPWM_GRP_CNT_TR_OUT_SEL_t*) 0x40381A54UL)
#define CYREG_TCPWM0_GRP0_CNT52_INTR    ((volatile un_TCPWM_GRP_CNT_INTR_t*) 0x40381A70UL)
#define CYREG_TCPWM0_GRP0_CNT52_INTR_SET ((volatile un_TCPWM_GRP_CNT_INTR_SET_t*) 0x40381A74UL)
#define CYREG_TCPWM0_GRP0_CNT52_INTR_MASK ((volatile un_TCPWM_GRP_CNT_INTR_MASK_t*) 0x40381A78UL)
#define CYREG_TCPWM0_GRP0_CNT52_INTR_MASKED ((volatile un_TCPWM_GRP_CNT_INTR_MASKED_t*) 0x40381A7CUL)

/**
  * \brief Timer/Counter/PWM Counter Module (TCPWM_GRP_CNT53)
  */
#define CYREG_TCPWM0_GRP0_CNT53_CTRL    ((volatile un_TCPWM_GRP_CNT_CTRL_t*) 0x40381A80UL)
#define CYREG_TCPWM0_GRP0_CNT53_STATUS  ((volatile un_TCPWM_GRP_CNT_STATUS_t*) 0x40381A84UL)
#define CYREG_TCPWM0_GRP0_CNT53_COUNTER ((volatile un_TCPWM_GRP_CNT_COUNTER_t*) 0x40381A88UL)
#define CYREG_TCPWM0_GRP0_CNT53_CC0     ((volatile un_TCPWM_GRP_CNT_CC0_t*) 0x40381A90UL)
#define CYREG_TCPWM0_GRP0_CNT53_CC0_BUFF ((volatile un_TCPWM_GRP_CNT_CC0_BUFF_t*) 0x40381A94UL)
#define CYREG_TCPWM0_GRP0_CNT53_CC1     ((volatile un_TCPWM_GRP_CNT_CC1_t*) 0x40381A98UL)
#define CYREG_TCPWM0_GRP0_CNT53_CC1_BUFF ((volatile un_TCPWM_GRP_CNT_CC1_BUFF_t*) 0x40381A9CUL)
#define CYREG_TCPWM0_GRP0_CNT53_PERIOD  ((volatile un_TCPWM_GRP_CNT_PERIOD_t*) 0x40381AA0UL)
#define CYREG_TCPWM0_GRP0_CNT53_PERIOD_BUFF ((volatile un_TCPWM_GRP_CNT_PERIOD_BUFF_t*) 0x40381AA4UL)
#define CYREG_TCPWM0_GRP0_CNT53_DT      ((volatile un_TCPWM_GRP_CNT_DT_t*) 0x40381AB0UL)
#define CYREG_TCPWM0_GRP0_CNT53_TR_CMD  ((volatile un_TCPWM_GRP_CNT_TR_CMD_t*) 0x40381AC0UL)
#define CYREG_TCPWM0_GRP0_CNT53_TR_IN_SEL0 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL0_t*) 0x40381AC4UL)
#define CYREG_TCPWM0_GRP0_CNT53_TR_IN_SEL1 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL1_t*) 0x40381AC8UL)
#define CYREG_TCPWM0_GRP0_CNT53_TR_IN_EDGE_SEL ((volatile un_TCPWM_GRP_CNT_TR_IN_EDGE_SEL_t*) 0x40381ACCUL)
#define CYREG_TCPWM0_GRP0_CNT53_TR_PWM_CTRL ((volatile un_TCPWM_GRP_CNT_TR_PWM_CTRL_t*) 0x40381AD0UL)
#define CYREG_TCPWM0_GRP0_CNT53_TR_OUT_SEL ((volatile un_TCPWM_GRP_CNT_TR_OUT_SEL_t*) 0x40381AD4UL)
#define CYREG_TCPWM0_GRP0_CNT53_INTR    ((volatile un_TCPWM_GRP_CNT_INTR_t*) 0x40381AF0UL)
#define CYREG_TCPWM0_GRP0_CNT53_INTR_SET ((volatile un_TCPWM_GRP_CNT_INTR_SET_t*) 0x40381AF4UL)
#define CYREG_TCPWM0_GRP0_CNT53_INTR_MASK ((volatile un_TCPWM_GRP_CNT_INTR_MASK_t*) 0x40381AF8UL)
#define CYREG_TCPWM0_GRP0_CNT53_INTR_MASKED ((volatile un_TCPWM_GRP_CNT_INTR_MASKED_t*) 0x40381AFCUL)

/**
  * \brief Timer/Counter/PWM Counter Module (TCPWM_GRP_CNT54)
  */
#define CYREG_TCPWM0_GRP0_CNT54_CTRL    ((volatile un_TCPWM_GRP_CNT_CTRL_t*) 0x40381B00UL)
#define CYREG_TCPWM0_GRP0_CNT54_STATUS  ((volatile un_TCPWM_GRP_CNT_STATUS_t*) 0x40381B04UL)
#define CYREG_TCPWM0_GRP0_CNT54_COUNTER ((volatile un_TCPWM_GRP_CNT_COUNTER_t*) 0x40381B08UL)
#define CYREG_TCPWM0_GRP0_CNT54_CC0     ((volatile un_TCPWM_GRP_CNT_CC0_t*) 0x40381B10UL)
#define CYREG_TCPWM0_GRP0_CNT54_CC0_BUFF ((volatile un_TCPWM_GRP_CNT_CC0_BUFF_t*) 0x40381B14UL)
#define CYREG_TCPWM0_GRP0_CNT54_CC1     ((volatile un_TCPWM_GRP_CNT_CC1_t*) 0x40381B18UL)
#define CYREG_TCPWM0_GRP0_CNT54_CC1_BUFF ((volatile un_TCPWM_GRP_CNT_CC1_BUFF_t*) 0x40381B1CUL)
#define CYREG_TCPWM0_GRP0_CNT54_PERIOD  ((volatile un_TCPWM_GRP_CNT_PERIOD_t*) 0x40381B20UL)
#define CYREG_TCPWM0_GRP0_CNT54_PERIOD_BUFF ((volatile un_TCPWM_GRP_CNT_PERIOD_BUFF_t*) 0x40381B24UL)
#define CYREG_TCPWM0_GRP0_CNT54_DT      ((volatile un_TCPWM_GRP_CNT_DT_t*) 0x40381B30UL)
#define CYREG_TCPWM0_GRP0_CNT54_TR_CMD  ((volatile un_TCPWM_GRP_CNT_TR_CMD_t*) 0x40381B40UL)
#define CYREG_TCPWM0_GRP0_CNT54_TR_IN_SEL0 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL0_t*) 0x40381B44UL)
#define CYREG_TCPWM0_GRP0_CNT54_TR_IN_SEL1 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL1_t*) 0x40381B48UL)
#define CYREG_TCPWM0_GRP0_CNT54_TR_IN_EDGE_SEL ((volatile un_TCPWM_GRP_CNT_TR_IN_EDGE_SEL_t*) 0x40381B4CUL)
#define CYREG_TCPWM0_GRP0_CNT54_TR_PWM_CTRL ((volatile un_TCPWM_GRP_CNT_TR_PWM_CTRL_t*) 0x40381B50UL)
#define CYREG_TCPWM0_GRP0_CNT54_TR_OUT_SEL ((volatile un_TCPWM_GRP_CNT_TR_OUT_SEL_t*) 0x40381B54UL)
#define CYREG_TCPWM0_GRP0_CNT54_INTR    ((volatile un_TCPWM_GRP_CNT_INTR_t*) 0x40381B70UL)
#define CYREG_TCPWM0_GRP0_CNT54_INTR_SET ((volatile un_TCPWM_GRP_CNT_INTR_SET_t*) 0x40381B74UL)
#define CYREG_TCPWM0_GRP0_CNT54_INTR_MASK ((volatile un_TCPWM_GRP_CNT_INTR_MASK_t*) 0x40381B78UL)
#define CYREG_TCPWM0_GRP0_CNT54_INTR_MASKED ((volatile un_TCPWM_GRP_CNT_INTR_MASKED_t*) 0x40381B7CUL)

/**
  * \brief Timer/Counter/PWM Counter Module (TCPWM_GRP_CNT55)
  */
#define CYREG_TCPWM0_GRP0_CNT55_CTRL    ((volatile un_TCPWM_GRP_CNT_CTRL_t*) 0x40381B80UL)
#define CYREG_TCPWM0_GRP0_CNT55_STATUS  ((volatile un_TCPWM_GRP_CNT_STATUS_t*) 0x40381B84UL)
#define CYREG_TCPWM0_GRP0_CNT55_COUNTER ((volatile un_TCPWM_GRP_CNT_COUNTER_t*) 0x40381B88UL)
#define CYREG_TCPWM0_GRP0_CNT55_CC0     ((volatile un_TCPWM_GRP_CNT_CC0_t*) 0x40381B90UL)
#define CYREG_TCPWM0_GRP0_CNT55_CC0_BUFF ((volatile un_TCPWM_GRP_CNT_CC0_BUFF_t*) 0x40381B94UL)
#define CYREG_TCPWM0_GRP0_CNT55_CC1     ((volatile un_TCPWM_GRP_CNT_CC1_t*) 0x40381B98UL)
#define CYREG_TCPWM0_GRP0_CNT55_CC1_BUFF ((volatile un_TCPWM_GRP_CNT_CC1_BUFF_t*) 0x40381B9CUL)
#define CYREG_TCPWM0_GRP0_CNT55_PERIOD  ((volatile un_TCPWM_GRP_CNT_PERIOD_t*) 0x40381BA0UL)
#define CYREG_TCPWM0_GRP0_CNT55_PERIOD_BUFF ((volatile un_TCPWM_GRP_CNT_PERIOD_BUFF_t*) 0x40381BA4UL)
#define CYREG_TCPWM0_GRP0_CNT55_DT      ((volatile un_TCPWM_GRP_CNT_DT_t*) 0x40381BB0UL)
#define CYREG_TCPWM0_GRP0_CNT55_TR_CMD  ((volatile un_TCPWM_GRP_CNT_TR_CMD_t*) 0x40381BC0UL)
#define CYREG_TCPWM0_GRP0_CNT55_TR_IN_SEL0 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL0_t*) 0x40381BC4UL)
#define CYREG_TCPWM0_GRP0_CNT55_TR_IN_SEL1 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL1_t*) 0x40381BC8UL)
#define CYREG_TCPWM0_GRP0_CNT55_TR_IN_EDGE_SEL ((volatile un_TCPWM_GRP_CNT_TR_IN_EDGE_SEL_t*) 0x40381BCCUL)
#define CYREG_TCPWM0_GRP0_CNT55_TR_PWM_CTRL ((volatile un_TCPWM_GRP_CNT_TR_PWM_CTRL_t*) 0x40381BD0UL)
#define CYREG_TCPWM0_GRP0_CNT55_TR_OUT_SEL ((volatile un_TCPWM_GRP_CNT_TR_OUT_SEL_t*) 0x40381BD4UL)
#define CYREG_TCPWM0_GRP0_CNT55_INTR    ((volatile un_TCPWM_GRP_CNT_INTR_t*) 0x40381BF0UL)
#define CYREG_TCPWM0_GRP0_CNT55_INTR_SET ((volatile un_TCPWM_GRP_CNT_INTR_SET_t*) 0x40381BF4UL)
#define CYREG_TCPWM0_GRP0_CNT55_INTR_MASK ((volatile un_TCPWM_GRP_CNT_INTR_MASK_t*) 0x40381BF8UL)
#define CYREG_TCPWM0_GRP0_CNT55_INTR_MASKED ((volatile un_TCPWM_GRP_CNT_INTR_MASKED_t*) 0x40381BFCUL)

/**
  * \brief Timer/Counter/PWM Counter Module (TCPWM_GRP_CNT56)
  */
#define CYREG_TCPWM0_GRP0_CNT56_CTRL    ((volatile un_TCPWM_GRP_CNT_CTRL_t*) 0x40381C00UL)
#define CYREG_TCPWM0_GRP0_CNT56_STATUS  ((volatile un_TCPWM_GRP_CNT_STATUS_t*) 0x40381C04UL)
#define CYREG_TCPWM0_GRP0_CNT56_COUNTER ((volatile un_TCPWM_GRP_CNT_COUNTER_t*) 0x40381C08UL)
#define CYREG_TCPWM0_GRP0_CNT56_CC0     ((volatile un_TCPWM_GRP_CNT_CC0_t*) 0x40381C10UL)
#define CYREG_TCPWM0_GRP0_CNT56_CC0_BUFF ((volatile un_TCPWM_GRP_CNT_CC0_BUFF_t*) 0x40381C14UL)
#define CYREG_TCPWM0_GRP0_CNT56_CC1     ((volatile un_TCPWM_GRP_CNT_CC1_t*) 0x40381C18UL)
#define CYREG_TCPWM0_GRP0_CNT56_CC1_BUFF ((volatile un_TCPWM_GRP_CNT_CC1_BUFF_t*) 0x40381C1CUL)
#define CYREG_TCPWM0_GRP0_CNT56_PERIOD  ((volatile un_TCPWM_GRP_CNT_PERIOD_t*) 0x40381C20UL)
#define CYREG_TCPWM0_GRP0_CNT56_PERIOD_BUFF ((volatile un_TCPWM_GRP_CNT_PERIOD_BUFF_t*) 0x40381C24UL)
#define CYREG_TCPWM0_GRP0_CNT56_DT      ((volatile un_TCPWM_GRP_CNT_DT_t*) 0x40381C30UL)
#define CYREG_TCPWM0_GRP0_CNT56_TR_CMD  ((volatile un_TCPWM_GRP_CNT_TR_CMD_t*) 0x40381C40UL)
#define CYREG_TCPWM0_GRP0_CNT56_TR_IN_SEL0 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL0_t*) 0x40381C44UL)
#define CYREG_TCPWM0_GRP0_CNT56_TR_IN_SEL1 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL1_t*) 0x40381C48UL)
#define CYREG_TCPWM0_GRP0_CNT56_TR_IN_EDGE_SEL ((volatile un_TCPWM_GRP_CNT_TR_IN_EDGE_SEL_t*) 0x40381C4CUL)
#define CYREG_TCPWM0_GRP0_CNT56_TR_PWM_CTRL ((volatile un_TCPWM_GRP_CNT_TR_PWM_CTRL_t*) 0x40381C50UL)
#define CYREG_TCPWM0_GRP0_CNT56_TR_OUT_SEL ((volatile un_TCPWM_GRP_CNT_TR_OUT_SEL_t*) 0x40381C54UL)
#define CYREG_TCPWM0_GRP0_CNT56_INTR    ((volatile un_TCPWM_GRP_CNT_INTR_t*) 0x40381C70UL)
#define CYREG_TCPWM0_GRP0_CNT56_INTR_SET ((volatile un_TCPWM_GRP_CNT_INTR_SET_t*) 0x40381C74UL)
#define CYREG_TCPWM0_GRP0_CNT56_INTR_MASK ((volatile un_TCPWM_GRP_CNT_INTR_MASK_t*) 0x40381C78UL)
#define CYREG_TCPWM0_GRP0_CNT56_INTR_MASKED ((volatile un_TCPWM_GRP_CNT_INTR_MASKED_t*) 0x40381C7CUL)

/**
  * \brief Timer/Counter/PWM Counter Module (TCPWM_GRP_CNT57)
  */
#define CYREG_TCPWM0_GRP0_CNT57_CTRL    ((volatile un_TCPWM_GRP_CNT_CTRL_t*) 0x40381C80UL)
#define CYREG_TCPWM0_GRP0_CNT57_STATUS  ((volatile un_TCPWM_GRP_CNT_STATUS_t*) 0x40381C84UL)
#define CYREG_TCPWM0_GRP0_CNT57_COUNTER ((volatile un_TCPWM_GRP_CNT_COUNTER_t*) 0x40381C88UL)
#define CYREG_TCPWM0_GRP0_CNT57_CC0     ((volatile un_TCPWM_GRP_CNT_CC0_t*) 0x40381C90UL)
#define CYREG_TCPWM0_GRP0_CNT57_CC0_BUFF ((volatile un_TCPWM_GRP_CNT_CC0_BUFF_t*) 0x40381C94UL)
#define CYREG_TCPWM0_GRP0_CNT57_CC1     ((volatile un_TCPWM_GRP_CNT_CC1_t*) 0x40381C98UL)
#define CYREG_TCPWM0_GRP0_CNT57_CC1_BUFF ((volatile un_TCPWM_GRP_CNT_CC1_BUFF_t*) 0x40381C9CUL)
#define CYREG_TCPWM0_GRP0_CNT57_PERIOD  ((volatile un_TCPWM_GRP_CNT_PERIOD_t*) 0x40381CA0UL)
#define CYREG_TCPWM0_GRP0_CNT57_PERIOD_BUFF ((volatile un_TCPWM_GRP_CNT_PERIOD_BUFF_t*) 0x40381CA4UL)
#define CYREG_TCPWM0_GRP0_CNT57_DT      ((volatile un_TCPWM_GRP_CNT_DT_t*) 0x40381CB0UL)
#define CYREG_TCPWM0_GRP0_CNT57_TR_CMD  ((volatile un_TCPWM_GRP_CNT_TR_CMD_t*) 0x40381CC0UL)
#define CYREG_TCPWM0_GRP0_CNT57_TR_IN_SEL0 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL0_t*) 0x40381CC4UL)
#define CYREG_TCPWM0_GRP0_CNT57_TR_IN_SEL1 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL1_t*) 0x40381CC8UL)
#define CYREG_TCPWM0_GRP0_CNT57_TR_IN_EDGE_SEL ((volatile un_TCPWM_GRP_CNT_TR_IN_EDGE_SEL_t*) 0x40381CCCUL)
#define CYREG_TCPWM0_GRP0_CNT57_TR_PWM_CTRL ((volatile un_TCPWM_GRP_CNT_TR_PWM_CTRL_t*) 0x40381CD0UL)
#define CYREG_TCPWM0_GRP0_CNT57_TR_OUT_SEL ((volatile un_TCPWM_GRP_CNT_TR_OUT_SEL_t*) 0x40381CD4UL)
#define CYREG_TCPWM0_GRP0_CNT57_INTR    ((volatile un_TCPWM_GRP_CNT_INTR_t*) 0x40381CF0UL)
#define CYREG_TCPWM0_GRP0_CNT57_INTR_SET ((volatile un_TCPWM_GRP_CNT_INTR_SET_t*) 0x40381CF4UL)
#define CYREG_TCPWM0_GRP0_CNT57_INTR_MASK ((volatile un_TCPWM_GRP_CNT_INTR_MASK_t*) 0x40381CF8UL)
#define CYREG_TCPWM0_GRP0_CNT57_INTR_MASKED ((volatile un_TCPWM_GRP_CNT_INTR_MASKED_t*) 0x40381CFCUL)

/**
  * \brief Timer/Counter/PWM Counter Module (TCPWM_GRP_CNT58)
  */
#define CYREG_TCPWM0_GRP0_CNT58_CTRL    ((volatile un_TCPWM_GRP_CNT_CTRL_t*) 0x40381D00UL)
#define CYREG_TCPWM0_GRP0_CNT58_STATUS  ((volatile un_TCPWM_GRP_CNT_STATUS_t*) 0x40381D04UL)
#define CYREG_TCPWM0_GRP0_CNT58_COUNTER ((volatile un_TCPWM_GRP_CNT_COUNTER_t*) 0x40381D08UL)
#define CYREG_TCPWM0_GRP0_CNT58_CC0     ((volatile un_TCPWM_GRP_CNT_CC0_t*) 0x40381D10UL)
#define CYREG_TCPWM0_GRP0_CNT58_CC0_BUFF ((volatile un_TCPWM_GRP_CNT_CC0_BUFF_t*) 0x40381D14UL)
#define CYREG_TCPWM0_GRP0_CNT58_CC1     ((volatile un_TCPWM_GRP_CNT_CC1_t*) 0x40381D18UL)
#define CYREG_TCPWM0_GRP0_CNT58_CC1_BUFF ((volatile un_TCPWM_GRP_CNT_CC1_BUFF_t*) 0x40381D1CUL)
#define CYREG_TCPWM0_GRP0_CNT58_PERIOD  ((volatile un_TCPWM_GRP_CNT_PERIOD_t*) 0x40381D20UL)
#define CYREG_TCPWM0_GRP0_CNT58_PERIOD_BUFF ((volatile un_TCPWM_GRP_CNT_PERIOD_BUFF_t*) 0x40381D24UL)
#define CYREG_TCPWM0_GRP0_CNT58_DT      ((volatile un_TCPWM_GRP_CNT_DT_t*) 0x40381D30UL)
#define CYREG_TCPWM0_GRP0_CNT58_TR_CMD  ((volatile un_TCPWM_GRP_CNT_TR_CMD_t*) 0x40381D40UL)
#define CYREG_TCPWM0_GRP0_CNT58_TR_IN_SEL0 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL0_t*) 0x40381D44UL)
#define CYREG_TCPWM0_GRP0_CNT58_TR_IN_SEL1 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL1_t*) 0x40381D48UL)
#define CYREG_TCPWM0_GRP0_CNT58_TR_IN_EDGE_SEL ((volatile un_TCPWM_GRP_CNT_TR_IN_EDGE_SEL_t*) 0x40381D4CUL)
#define CYREG_TCPWM0_GRP0_CNT58_TR_PWM_CTRL ((volatile un_TCPWM_GRP_CNT_TR_PWM_CTRL_t*) 0x40381D50UL)
#define CYREG_TCPWM0_GRP0_CNT58_TR_OUT_SEL ((volatile un_TCPWM_GRP_CNT_TR_OUT_SEL_t*) 0x40381D54UL)
#define CYREG_TCPWM0_GRP0_CNT58_INTR    ((volatile un_TCPWM_GRP_CNT_INTR_t*) 0x40381D70UL)
#define CYREG_TCPWM0_GRP0_CNT58_INTR_SET ((volatile un_TCPWM_GRP_CNT_INTR_SET_t*) 0x40381D74UL)
#define CYREG_TCPWM0_GRP0_CNT58_INTR_MASK ((volatile un_TCPWM_GRP_CNT_INTR_MASK_t*) 0x40381D78UL)
#define CYREG_TCPWM0_GRP0_CNT58_INTR_MASKED ((volatile un_TCPWM_GRP_CNT_INTR_MASKED_t*) 0x40381D7CUL)

/**
  * \brief Timer/Counter/PWM Counter Module (TCPWM_GRP_CNT59)
  */
#define CYREG_TCPWM0_GRP0_CNT59_CTRL    ((volatile un_TCPWM_GRP_CNT_CTRL_t*) 0x40381D80UL)
#define CYREG_TCPWM0_GRP0_CNT59_STATUS  ((volatile un_TCPWM_GRP_CNT_STATUS_t*) 0x40381D84UL)
#define CYREG_TCPWM0_GRP0_CNT59_COUNTER ((volatile un_TCPWM_GRP_CNT_COUNTER_t*) 0x40381D88UL)
#define CYREG_TCPWM0_GRP0_CNT59_CC0     ((volatile un_TCPWM_GRP_CNT_CC0_t*) 0x40381D90UL)
#define CYREG_TCPWM0_GRP0_CNT59_CC0_BUFF ((volatile un_TCPWM_GRP_CNT_CC0_BUFF_t*) 0x40381D94UL)
#define CYREG_TCPWM0_GRP0_CNT59_CC1     ((volatile un_TCPWM_GRP_CNT_CC1_t*) 0x40381D98UL)
#define CYREG_TCPWM0_GRP0_CNT59_CC1_BUFF ((volatile un_TCPWM_GRP_CNT_CC1_BUFF_t*) 0x40381D9CUL)
#define CYREG_TCPWM0_GRP0_CNT59_PERIOD  ((volatile un_TCPWM_GRP_CNT_PERIOD_t*) 0x40381DA0UL)
#define CYREG_TCPWM0_GRP0_CNT59_PERIOD_BUFF ((volatile un_TCPWM_GRP_CNT_PERIOD_BUFF_t*) 0x40381DA4UL)
#define CYREG_TCPWM0_GRP0_CNT59_DT      ((volatile un_TCPWM_GRP_CNT_DT_t*) 0x40381DB0UL)
#define CYREG_TCPWM0_GRP0_CNT59_TR_CMD  ((volatile un_TCPWM_GRP_CNT_TR_CMD_t*) 0x40381DC0UL)
#define CYREG_TCPWM0_GRP0_CNT59_TR_IN_SEL0 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL0_t*) 0x40381DC4UL)
#define CYREG_TCPWM0_GRP0_CNT59_TR_IN_SEL1 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL1_t*) 0x40381DC8UL)
#define CYREG_TCPWM0_GRP0_CNT59_TR_IN_EDGE_SEL ((volatile un_TCPWM_GRP_CNT_TR_IN_EDGE_SEL_t*) 0x40381DCCUL)
#define CYREG_TCPWM0_GRP0_CNT59_TR_PWM_CTRL ((volatile un_TCPWM_GRP_CNT_TR_PWM_CTRL_t*) 0x40381DD0UL)
#define CYREG_TCPWM0_GRP0_CNT59_TR_OUT_SEL ((volatile un_TCPWM_GRP_CNT_TR_OUT_SEL_t*) 0x40381DD4UL)
#define CYREG_TCPWM0_GRP0_CNT59_INTR    ((volatile un_TCPWM_GRP_CNT_INTR_t*) 0x40381DF0UL)
#define CYREG_TCPWM0_GRP0_CNT59_INTR_SET ((volatile un_TCPWM_GRP_CNT_INTR_SET_t*) 0x40381DF4UL)
#define CYREG_TCPWM0_GRP0_CNT59_INTR_MASK ((volatile un_TCPWM_GRP_CNT_INTR_MASK_t*) 0x40381DF8UL)
#define CYREG_TCPWM0_GRP0_CNT59_INTR_MASKED ((volatile un_TCPWM_GRP_CNT_INTR_MASKED_t*) 0x40381DFCUL)

/**
  * \brief Timer/Counter/PWM Counter Module (TCPWM_GRP_CNT60)
  */
#define CYREG_TCPWM0_GRP0_CNT60_CTRL    ((volatile un_TCPWM_GRP_CNT_CTRL_t*) 0x40381E00UL)
#define CYREG_TCPWM0_GRP0_CNT60_STATUS  ((volatile un_TCPWM_GRP_CNT_STATUS_t*) 0x40381E04UL)
#define CYREG_TCPWM0_GRP0_CNT60_COUNTER ((volatile un_TCPWM_GRP_CNT_COUNTER_t*) 0x40381E08UL)
#define CYREG_TCPWM0_GRP0_CNT60_CC0     ((volatile un_TCPWM_GRP_CNT_CC0_t*) 0x40381E10UL)
#define CYREG_TCPWM0_GRP0_CNT60_CC0_BUFF ((volatile un_TCPWM_GRP_CNT_CC0_BUFF_t*) 0x40381E14UL)
#define CYREG_TCPWM0_GRP0_CNT60_CC1     ((volatile un_TCPWM_GRP_CNT_CC1_t*) 0x40381E18UL)
#define CYREG_TCPWM0_GRP0_CNT60_CC1_BUFF ((volatile un_TCPWM_GRP_CNT_CC1_BUFF_t*) 0x40381E1CUL)
#define CYREG_TCPWM0_GRP0_CNT60_PERIOD  ((volatile un_TCPWM_GRP_CNT_PERIOD_t*) 0x40381E20UL)
#define CYREG_TCPWM0_GRP0_CNT60_PERIOD_BUFF ((volatile un_TCPWM_GRP_CNT_PERIOD_BUFF_t*) 0x40381E24UL)
#define CYREG_TCPWM0_GRP0_CNT60_DT      ((volatile un_TCPWM_GRP_CNT_DT_t*) 0x40381E30UL)
#define CYREG_TCPWM0_GRP0_CNT60_TR_CMD  ((volatile un_TCPWM_GRP_CNT_TR_CMD_t*) 0x40381E40UL)
#define CYREG_TCPWM0_GRP0_CNT60_TR_IN_SEL0 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL0_t*) 0x40381E44UL)
#define CYREG_TCPWM0_GRP0_CNT60_TR_IN_SEL1 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL1_t*) 0x40381E48UL)
#define CYREG_TCPWM0_GRP0_CNT60_TR_IN_EDGE_SEL ((volatile un_TCPWM_GRP_CNT_TR_IN_EDGE_SEL_t*) 0x40381E4CUL)
#define CYREG_TCPWM0_GRP0_CNT60_TR_PWM_CTRL ((volatile un_TCPWM_GRP_CNT_TR_PWM_CTRL_t*) 0x40381E50UL)
#define CYREG_TCPWM0_GRP0_CNT60_TR_OUT_SEL ((volatile un_TCPWM_GRP_CNT_TR_OUT_SEL_t*) 0x40381E54UL)
#define CYREG_TCPWM0_GRP0_CNT60_INTR    ((volatile un_TCPWM_GRP_CNT_INTR_t*) 0x40381E70UL)
#define CYREG_TCPWM0_GRP0_CNT60_INTR_SET ((volatile un_TCPWM_GRP_CNT_INTR_SET_t*) 0x40381E74UL)
#define CYREG_TCPWM0_GRP0_CNT60_INTR_MASK ((volatile un_TCPWM_GRP_CNT_INTR_MASK_t*) 0x40381E78UL)
#define CYREG_TCPWM0_GRP0_CNT60_INTR_MASKED ((volatile un_TCPWM_GRP_CNT_INTR_MASKED_t*) 0x40381E7CUL)

/**
  * \brief Timer/Counter/PWM Counter Module (TCPWM_GRP_CNT61)
  */
#define CYREG_TCPWM0_GRP0_CNT61_CTRL    ((volatile un_TCPWM_GRP_CNT_CTRL_t*) 0x40381E80UL)
#define CYREG_TCPWM0_GRP0_CNT61_STATUS  ((volatile un_TCPWM_GRP_CNT_STATUS_t*) 0x40381E84UL)
#define CYREG_TCPWM0_GRP0_CNT61_COUNTER ((volatile un_TCPWM_GRP_CNT_COUNTER_t*) 0x40381E88UL)
#define CYREG_TCPWM0_GRP0_CNT61_CC0     ((volatile un_TCPWM_GRP_CNT_CC0_t*) 0x40381E90UL)
#define CYREG_TCPWM0_GRP0_CNT61_CC0_BUFF ((volatile un_TCPWM_GRP_CNT_CC0_BUFF_t*) 0x40381E94UL)
#define CYREG_TCPWM0_GRP0_CNT61_CC1     ((volatile un_TCPWM_GRP_CNT_CC1_t*) 0x40381E98UL)
#define CYREG_TCPWM0_GRP0_CNT61_CC1_BUFF ((volatile un_TCPWM_GRP_CNT_CC1_BUFF_t*) 0x40381E9CUL)
#define CYREG_TCPWM0_GRP0_CNT61_PERIOD  ((volatile un_TCPWM_GRP_CNT_PERIOD_t*) 0x40381EA0UL)
#define CYREG_TCPWM0_GRP0_CNT61_PERIOD_BUFF ((volatile un_TCPWM_GRP_CNT_PERIOD_BUFF_t*) 0x40381EA4UL)
#define CYREG_TCPWM0_GRP0_CNT61_DT      ((volatile un_TCPWM_GRP_CNT_DT_t*) 0x40381EB0UL)
#define CYREG_TCPWM0_GRP0_CNT61_TR_CMD  ((volatile un_TCPWM_GRP_CNT_TR_CMD_t*) 0x40381EC0UL)
#define CYREG_TCPWM0_GRP0_CNT61_TR_IN_SEL0 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL0_t*) 0x40381EC4UL)
#define CYREG_TCPWM0_GRP0_CNT61_TR_IN_SEL1 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL1_t*) 0x40381EC8UL)
#define CYREG_TCPWM0_GRP0_CNT61_TR_IN_EDGE_SEL ((volatile un_TCPWM_GRP_CNT_TR_IN_EDGE_SEL_t*) 0x40381ECCUL)
#define CYREG_TCPWM0_GRP0_CNT61_TR_PWM_CTRL ((volatile un_TCPWM_GRP_CNT_TR_PWM_CTRL_t*) 0x40381ED0UL)
#define CYREG_TCPWM0_GRP0_CNT61_TR_OUT_SEL ((volatile un_TCPWM_GRP_CNT_TR_OUT_SEL_t*) 0x40381ED4UL)
#define CYREG_TCPWM0_GRP0_CNT61_INTR    ((volatile un_TCPWM_GRP_CNT_INTR_t*) 0x40381EF0UL)
#define CYREG_TCPWM0_GRP0_CNT61_INTR_SET ((volatile un_TCPWM_GRP_CNT_INTR_SET_t*) 0x40381EF4UL)
#define CYREG_TCPWM0_GRP0_CNT61_INTR_MASK ((volatile un_TCPWM_GRP_CNT_INTR_MASK_t*) 0x40381EF8UL)
#define CYREG_TCPWM0_GRP0_CNT61_INTR_MASKED ((volatile un_TCPWM_GRP_CNT_INTR_MASKED_t*) 0x40381EFCUL)

/**
  * \brief Timer/Counter/PWM Counter Module (TCPWM_GRP_CNT62)
  */
#define CYREG_TCPWM0_GRP0_CNT62_CTRL    ((volatile un_TCPWM_GRP_CNT_CTRL_t*) 0x40381F00UL)
#define CYREG_TCPWM0_GRP0_CNT62_STATUS  ((volatile un_TCPWM_GRP_CNT_STATUS_t*) 0x40381F04UL)
#define CYREG_TCPWM0_GRP0_CNT62_COUNTER ((volatile un_TCPWM_GRP_CNT_COUNTER_t*) 0x40381F08UL)
#define CYREG_TCPWM0_GRP0_CNT62_CC0     ((volatile un_TCPWM_GRP_CNT_CC0_t*) 0x40381F10UL)
#define CYREG_TCPWM0_GRP0_CNT62_CC0_BUFF ((volatile un_TCPWM_GRP_CNT_CC0_BUFF_t*) 0x40381F14UL)
#define CYREG_TCPWM0_GRP0_CNT62_CC1     ((volatile un_TCPWM_GRP_CNT_CC1_t*) 0x40381F18UL)
#define CYREG_TCPWM0_GRP0_CNT62_CC1_BUFF ((volatile un_TCPWM_GRP_CNT_CC1_BUFF_t*) 0x40381F1CUL)
#define CYREG_TCPWM0_GRP0_CNT62_PERIOD  ((volatile un_TCPWM_GRP_CNT_PERIOD_t*) 0x40381F20UL)
#define CYREG_TCPWM0_GRP0_CNT62_PERIOD_BUFF ((volatile un_TCPWM_GRP_CNT_PERIOD_BUFF_t*) 0x40381F24UL)
#define CYREG_TCPWM0_GRP0_CNT62_DT      ((volatile un_TCPWM_GRP_CNT_DT_t*) 0x40381F30UL)
#define CYREG_TCPWM0_GRP0_CNT62_TR_CMD  ((volatile un_TCPWM_GRP_CNT_TR_CMD_t*) 0x40381F40UL)
#define CYREG_TCPWM0_GRP0_CNT62_TR_IN_SEL0 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL0_t*) 0x40381F44UL)
#define CYREG_TCPWM0_GRP0_CNT62_TR_IN_SEL1 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL1_t*) 0x40381F48UL)
#define CYREG_TCPWM0_GRP0_CNT62_TR_IN_EDGE_SEL ((volatile un_TCPWM_GRP_CNT_TR_IN_EDGE_SEL_t*) 0x40381F4CUL)
#define CYREG_TCPWM0_GRP0_CNT62_TR_PWM_CTRL ((volatile un_TCPWM_GRP_CNT_TR_PWM_CTRL_t*) 0x40381F50UL)
#define CYREG_TCPWM0_GRP0_CNT62_TR_OUT_SEL ((volatile un_TCPWM_GRP_CNT_TR_OUT_SEL_t*) 0x40381F54UL)
#define CYREG_TCPWM0_GRP0_CNT62_INTR    ((volatile un_TCPWM_GRP_CNT_INTR_t*) 0x40381F70UL)
#define CYREG_TCPWM0_GRP0_CNT62_INTR_SET ((volatile un_TCPWM_GRP_CNT_INTR_SET_t*) 0x40381F74UL)
#define CYREG_TCPWM0_GRP0_CNT62_INTR_MASK ((volatile un_TCPWM_GRP_CNT_INTR_MASK_t*) 0x40381F78UL)
#define CYREG_TCPWM0_GRP0_CNT62_INTR_MASKED ((volatile un_TCPWM_GRP_CNT_INTR_MASKED_t*) 0x40381F7CUL)

/**
  * \brief Timer/Counter/PWM Counter Module (TCPWM_GRP_CNT0)
  */
#define CYREG_TCPWM0_GRP1_CNT0_CTRL     ((volatile un_TCPWM_GRP_CNT_CTRL_t*) 0x40388000UL)
#define CYREG_TCPWM0_GRP1_CNT0_STATUS   ((volatile un_TCPWM_GRP_CNT_STATUS_t*) 0x40388004UL)
#define CYREG_TCPWM0_GRP1_CNT0_COUNTER  ((volatile un_TCPWM_GRP_CNT_COUNTER_t*) 0x40388008UL)
#define CYREG_TCPWM0_GRP1_CNT0_CC0      ((volatile un_TCPWM_GRP_CNT_CC0_t*) 0x40388010UL)
#define CYREG_TCPWM0_GRP1_CNT0_CC0_BUFF ((volatile un_TCPWM_GRP_CNT_CC0_BUFF_t*) 0x40388014UL)
#define CYREG_TCPWM0_GRP1_CNT0_CC1      ((volatile un_TCPWM_GRP_CNT_CC1_t*) 0x40388018UL)
#define CYREG_TCPWM0_GRP1_CNT0_CC1_BUFF ((volatile un_TCPWM_GRP_CNT_CC1_BUFF_t*) 0x4038801CUL)
#define CYREG_TCPWM0_GRP1_CNT0_PERIOD   ((volatile un_TCPWM_GRP_CNT_PERIOD_t*) 0x40388020UL)
#define CYREG_TCPWM0_GRP1_CNT0_PERIOD_BUFF ((volatile un_TCPWM_GRP_CNT_PERIOD_BUFF_t*) 0x40388024UL)
#define CYREG_TCPWM0_GRP1_CNT0_LINE_SEL ((volatile un_TCPWM_GRP_CNT_LINE_SEL_t*) 0x40388028UL)
#define CYREG_TCPWM0_GRP1_CNT0_LINE_SEL_BUFF ((volatile un_TCPWM_GRP_CNT_LINE_SEL_BUFF_t*) 0x4038802CUL)
#define CYREG_TCPWM0_GRP1_CNT0_DT       ((volatile un_TCPWM_GRP_CNT_DT_t*) 0x40388030UL)
#define CYREG_TCPWM0_GRP1_CNT0_TR_CMD   ((volatile un_TCPWM_GRP_CNT_TR_CMD_t*) 0x40388040UL)
#define CYREG_TCPWM0_GRP1_CNT0_TR_IN_SEL0 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL0_t*) 0x40388044UL)
#define CYREG_TCPWM0_GRP1_CNT0_TR_IN_SEL1 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL1_t*) 0x40388048UL)
#define CYREG_TCPWM0_GRP1_CNT0_TR_IN_EDGE_SEL ((volatile un_TCPWM_GRP_CNT_TR_IN_EDGE_SEL_t*) 0x4038804CUL)
#define CYREG_TCPWM0_GRP1_CNT0_TR_PWM_CTRL ((volatile un_TCPWM_GRP_CNT_TR_PWM_CTRL_t*) 0x40388050UL)
#define CYREG_TCPWM0_GRP1_CNT0_TR_OUT_SEL ((volatile un_TCPWM_GRP_CNT_TR_OUT_SEL_t*) 0x40388054UL)
#define CYREG_TCPWM0_GRP1_CNT0_INTR     ((volatile un_TCPWM_GRP_CNT_INTR_t*) 0x40388070UL)
#define CYREG_TCPWM0_GRP1_CNT0_INTR_SET ((volatile un_TCPWM_GRP_CNT_INTR_SET_t*) 0x40388074UL)
#define CYREG_TCPWM0_GRP1_CNT0_INTR_MASK ((volatile un_TCPWM_GRP_CNT_INTR_MASK_t*) 0x40388078UL)
#define CYREG_TCPWM0_GRP1_CNT0_INTR_MASKED ((volatile un_TCPWM_GRP_CNT_INTR_MASKED_t*) 0x4038807CUL)

/**
  * \brief Timer/Counter/PWM Counter Module (TCPWM_GRP_CNT1)
  */
#define CYREG_TCPWM0_GRP1_CNT1_CTRL     ((volatile un_TCPWM_GRP_CNT_CTRL_t*) 0x40388080UL)
#define CYREG_TCPWM0_GRP1_CNT1_STATUS   ((volatile un_TCPWM_GRP_CNT_STATUS_t*) 0x40388084UL)
#define CYREG_TCPWM0_GRP1_CNT1_COUNTER  ((volatile un_TCPWM_GRP_CNT_COUNTER_t*) 0x40388088UL)
#define CYREG_TCPWM0_GRP1_CNT1_CC0      ((volatile un_TCPWM_GRP_CNT_CC0_t*) 0x40388090UL)
#define CYREG_TCPWM0_GRP1_CNT1_CC0_BUFF ((volatile un_TCPWM_GRP_CNT_CC0_BUFF_t*) 0x40388094UL)
#define CYREG_TCPWM0_GRP1_CNT1_CC1      ((volatile un_TCPWM_GRP_CNT_CC1_t*) 0x40388098UL)
#define CYREG_TCPWM0_GRP1_CNT1_CC1_BUFF ((volatile un_TCPWM_GRP_CNT_CC1_BUFF_t*) 0x4038809CUL)
#define CYREG_TCPWM0_GRP1_CNT1_PERIOD   ((volatile un_TCPWM_GRP_CNT_PERIOD_t*) 0x403880A0UL)
#define CYREG_TCPWM0_GRP1_CNT1_PERIOD_BUFF ((volatile un_TCPWM_GRP_CNT_PERIOD_BUFF_t*) 0x403880A4UL)
#define CYREG_TCPWM0_GRP1_CNT1_LINE_SEL ((volatile un_TCPWM_GRP_CNT_LINE_SEL_t*) 0x403880A8UL)
#define CYREG_TCPWM0_GRP1_CNT1_LINE_SEL_BUFF ((volatile un_TCPWM_GRP_CNT_LINE_SEL_BUFF_t*) 0x403880ACUL)
#define CYREG_TCPWM0_GRP1_CNT1_DT       ((volatile un_TCPWM_GRP_CNT_DT_t*) 0x403880B0UL)
#define CYREG_TCPWM0_GRP1_CNT1_TR_CMD   ((volatile un_TCPWM_GRP_CNT_TR_CMD_t*) 0x403880C0UL)
#define CYREG_TCPWM0_GRP1_CNT1_TR_IN_SEL0 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL0_t*) 0x403880C4UL)
#define CYREG_TCPWM0_GRP1_CNT1_TR_IN_SEL1 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL1_t*) 0x403880C8UL)
#define CYREG_TCPWM0_GRP1_CNT1_TR_IN_EDGE_SEL ((volatile un_TCPWM_GRP_CNT_TR_IN_EDGE_SEL_t*) 0x403880CCUL)
#define CYREG_TCPWM0_GRP1_CNT1_TR_PWM_CTRL ((volatile un_TCPWM_GRP_CNT_TR_PWM_CTRL_t*) 0x403880D0UL)
#define CYREG_TCPWM0_GRP1_CNT1_TR_OUT_SEL ((volatile un_TCPWM_GRP_CNT_TR_OUT_SEL_t*) 0x403880D4UL)
#define CYREG_TCPWM0_GRP1_CNT1_INTR     ((volatile un_TCPWM_GRP_CNT_INTR_t*) 0x403880F0UL)
#define CYREG_TCPWM0_GRP1_CNT1_INTR_SET ((volatile un_TCPWM_GRP_CNT_INTR_SET_t*) 0x403880F4UL)
#define CYREG_TCPWM0_GRP1_CNT1_INTR_MASK ((volatile un_TCPWM_GRP_CNT_INTR_MASK_t*) 0x403880F8UL)
#define CYREG_TCPWM0_GRP1_CNT1_INTR_MASKED ((volatile un_TCPWM_GRP_CNT_INTR_MASKED_t*) 0x403880FCUL)

/**
  * \brief Timer/Counter/PWM Counter Module (TCPWM_GRP_CNT2)
  */
#define CYREG_TCPWM0_GRP1_CNT2_CTRL     ((volatile un_TCPWM_GRP_CNT_CTRL_t*) 0x40388100UL)
#define CYREG_TCPWM0_GRP1_CNT2_STATUS   ((volatile un_TCPWM_GRP_CNT_STATUS_t*) 0x40388104UL)
#define CYREG_TCPWM0_GRP1_CNT2_COUNTER  ((volatile un_TCPWM_GRP_CNT_COUNTER_t*) 0x40388108UL)
#define CYREG_TCPWM0_GRP1_CNT2_CC0      ((volatile un_TCPWM_GRP_CNT_CC0_t*) 0x40388110UL)
#define CYREG_TCPWM0_GRP1_CNT2_CC0_BUFF ((volatile un_TCPWM_GRP_CNT_CC0_BUFF_t*) 0x40388114UL)
#define CYREG_TCPWM0_GRP1_CNT2_CC1      ((volatile un_TCPWM_GRP_CNT_CC1_t*) 0x40388118UL)
#define CYREG_TCPWM0_GRP1_CNT2_CC1_BUFF ((volatile un_TCPWM_GRP_CNT_CC1_BUFF_t*) 0x4038811CUL)
#define CYREG_TCPWM0_GRP1_CNT2_PERIOD   ((volatile un_TCPWM_GRP_CNT_PERIOD_t*) 0x40388120UL)
#define CYREG_TCPWM0_GRP1_CNT2_PERIOD_BUFF ((volatile un_TCPWM_GRP_CNT_PERIOD_BUFF_t*) 0x40388124UL)
#define CYREG_TCPWM0_GRP1_CNT2_LINE_SEL ((volatile un_TCPWM_GRP_CNT_LINE_SEL_t*) 0x40388128UL)
#define CYREG_TCPWM0_GRP1_CNT2_LINE_SEL_BUFF ((volatile un_TCPWM_GRP_CNT_LINE_SEL_BUFF_t*) 0x4038812CUL)
#define CYREG_TCPWM0_GRP1_CNT2_DT       ((volatile un_TCPWM_GRP_CNT_DT_t*) 0x40388130UL)
#define CYREG_TCPWM0_GRP1_CNT2_TR_CMD   ((volatile un_TCPWM_GRP_CNT_TR_CMD_t*) 0x40388140UL)
#define CYREG_TCPWM0_GRP1_CNT2_TR_IN_SEL0 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL0_t*) 0x40388144UL)
#define CYREG_TCPWM0_GRP1_CNT2_TR_IN_SEL1 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL1_t*) 0x40388148UL)
#define CYREG_TCPWM0_GRP1_CNT2_TR_IN_EDGE_SEL ((volatile un_TCPWM_GRP_CNT_TR_IN_EDGE_SEL_t*) 0x4038814CUL)
#define CYREG_TCPWM0_GRP1_CNT2_TR_PWM_CTRL ((volatile un_TCPWM_GRP_CNT_TR_PWM_CTRL_t*) 0x40388150UL)
#define CYREG_TCPWM0_GRP1_CNT2_TR_OUT_SEL ((volatile un_TCPWM_GRP_CNT_TR_OUT_SEL_t*) 0x40388154UL)
#define CYREG_TCPWM0_GRP1_CNT2_INTR     ((volatile un_TCPWM_GRP_CNT_INTR_t*) 0x40388170UL)
#define CYREG_TCPWM0_GRP1_CNT2_INTR_SET ((volatile un_TCPWM_GRP_CNT_INTR_SET_t*) 0x40388174UL)
#define CYREG_TCPWM0_GRP1_CNT2_INTR_MASK ((volatile un_TCPWM_GRP_CNT_INTR_MASK_t*) 0x40388178UL)
#define CYREG_TCPWM0_GRP1_CNT2_INTR_MASKED ((volatile un_TCPWM_GRP_CNT_INTR_MASKED_t*) 0x4038817CUL)

/**
  * \brief Timer/Counter/PWM Counter Module (TCPWM_GRP_CNT3)
  */
#define CYREG_TCPWM0_GRP1_CNT3_CTRL     ((volatile un_TCPWM_GRP_CNT_CTRL_t*) 0x40388180UL)
#define CYREG_TCPWM0_GRP1_CNT3_STATUS   ((volatile un_TCPWM_GRP_CNT_STATUS_t*) 0x40388184UL)
#define CYREG_TCPWM0_GRP1_CNT3_COUNTER  ((volatile un_TCPWM_GRP_CNT_COUNTER_t*) 0x40388188UL)
#define CYREG_TCPWM0_GRP1_CNT3_CC0      ((volatile un_TCPWM_GRP_CNT_CC0_t*) 0x40388190UL)
#define CYREG_TCPWM0_GRP1_CNT3_CC0_BUFF ((volatile un_TCPWM_GRP_CNT_CC0_BUFF_t*) 0x40388194UL)
#define CYREG_TCPWM0_GRP1_CNT3_CC1      ((volatile un_TCPWM_GRP_CNT_CC1_t*) 0x40388198UL)
#define CYREG_TCPWM0_GRP1_CNT3_CC1_BUFF ((volatile un_TCPWM_GRP_CNT_CC1_BUFF_t*) 0x4038819CUL)
#define CYREG_TCPWM0_GRP1_CNT3_PERIOD   ((volatile un_TCPWM_GRP_CNT_PERIOD_t*) 0x403881A0UL)
#define CYREG_TCPWM0_GRP1_CNT3_PERIOD_BUFF ((volatile un_TCPWM_GRP_CNT_PERIOD_BUFF_t*) 0x403881A4UL)
#define CYREG_TCPWM0_GRP1_CNT3_LINE_SEL ((volatile un_TCPWM_GRP_CNT_LINE_SEL_t*) 0x403881A8UL)
#define CYREG_TCPWM0_GRP1_CNT3_LINE_SEL_BUFF ((volatile un_TCPWM_GRP_CNT_LINE_SEL_BUFF_t*) 0x403881ACUL)
#define CYREG_TCPWM0_GRP1_CNT3_DT       ((volatile un_TCPWM_GRP_CNT_DT_t*) 0x403881B0UL)
#define CYREG_TCPWM0_GRP1_CNT3_TR_CMD   ((volatile un_TCPWM_GRP_CNT_TR_CMD_t*) 0x403881C0UL)
#define CYREG_TCPWM0_GRP1_CNT3_TR_IN_SEL0 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL0_t*) 0x403881C4UL)
#define CYREG_TCPWM0_GRP1_CNT3_TR_IN_SEL1 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL1_t*) 0x403881C8UL)
#define CYREG_TCPWM0_GRP1_CNT3_TR_IN_EDGE_SEL ((volatile un_TCPWM_GRP_CNT_TR_IN_EDGE_SEL_t*) 0x403881CCUL)
#define CYREG_TCPWM0_GRP1_CNT3_TR_PWM_CTRL ((volatile un_TCPWM_GRP_CNT_TR_PWM_CTRL_t*) 0x403881D0UL)
#define CYREG_TCPWM0_GRP1_CNT3_TR_OUT_SEL ((volatile un_TCPWM_GRP_CNT_TR_OUT_SEL_t*) 0x403881D4UL)
#define CYREG_TCPWM0_GRP1_CNT3_INTR     ((volatile un_TCPWM_GRP_CNT_INTR_t*) 0x403881F0UL)
#define CYREG_TCPWM0_GRP1_CNT3_INTR_SET ((volatile un_TCPWM_GRP_CNT_INTR_SET_t*) 0x403881F4UL)
#define CYREG_TCPWM0_GRP1_CNT3_INTR_MASK ((volatile un_TCPWM_GRP_CNT_INTR_MASK_t*) 0x403881F8UL)
#define CYREG_TCPWM0_GRP1_CNT3_INTR_MASKED ((volatile un_TCPWM_GRP_CNT_INTR_MASKED_t*) 0x403881FCUL)

/**
  * \brief Timer/Counter/PWM Counter Module (TCPWM_GRP_CNT4)
  */
#define CYREG_TCPWM0_GRP1_CNT4_CTRL     ((volatile un_TCPWM_GRP_CNT_CTRL_t*) 0x40388200UL)
#define CYREG_TCPWM0_GRP1_CNT4_STATUS   ((volatile un_TCPWM_GRP_CNT_STATUS_t*) 0x40388204UL)
#define CYREG_TCPWM0_GRP1_CNT4_COUNTER  ((volatile un_TCPWM_GRP_CNT_COUNTER_t*) 0x40388208UL)
#define CYREG_TCPWM0_GRP1_CNT4_CC0      ((volatile un_TCPWM_GRP_CNT_CC0_t*) 0x40388210UL)
#define CYREG_TCPWM0_GRP1_CNT4_CC0_BUFF ((volatile un_TCPWM_GRP_CNT_CC0_BUFF_t*) 0x40388214UL)
#define CYREG_TCPWM0_GRP1_CNT4_CC1      ((volatile un_TCPWM_GRP_CNT_CC1_t*) 0x40388218UL)
#define CYREG_TCPWM0_GRP1_CNT4_CC1_BUFF ((volatile un_TCPWM_GRP_CNT_CC1_BUFF_t*) 0x4038821CUL)
#define CYREG_TCPWM0_GRP1_CNT4_PERIOD   ((volatile un_TCPWM_GRP_CNT_PERIOD_t*) 0x40388220UL)
#define CYREG_TCPWM0_GRP1_CNT4_PERIOD_BUFF ((volatile un_TCPWM_GRP_CNT_PERIOD_BUFF_t*) 0x40388224UL)
#define CYREG_TCPWM0_GRP1_CNT4_LINE_SEL ((volatile un_TCPWM_GRP_CNT_LINE_SEL_t*) 0x40388228UL)
#define CYREG_TCPWM0_GRP1_CNT4_LINE_SEL_BUFF ((volatile un_TCPWM_GRP_CNT_LINE_SEL_BUFF_t*) 0x4038822CUL)
#define CYREG_TCPWM0_GRP1_CNT4_DT       ((volatile un_TCPWM_GRP_CNT_DT_t*) 0x40388230UL)
#define CYREG_TCPWM0_GRP1_CNT4_TR_CMD   ((volatile un_TCPWM_GRP_CNT_TR_CMD_t*) 0x40388240UL)
#define CYREG_TCPWM0_GRP1_CNT4_TR_IN_SEL0 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL0_t*) 0x40388244UL)
#define CYREG_TCPWM0_GRP1_CNT4_TR_IN_SEL1 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL1_t*) 0x40388248UL)
#define CYREG_TCPWM0_GRP1_CNT4_TR_IN_EDGE_SEL ((volatile un_TCPWM_GRP_CNT_TR_IN_EDGE_SEL_t*) 0x4038824CUL)
#define CYREG_TCPWM0_GRP1_CNT4_TR_PWM_CTRL ((volatile un_TCPWM_GRP_CNT_TR_PWM_CTRL_t*) 0x40388250UL)
#define CYREG_TCPWM0_GRP1_CNT4_TR_OUT_SEL ((volatile un_TCPWM_GRP_CNT_TR_OUT_SEL_t*) 0x40388254UL)
#define CYREG_TCPWM0_GRP1_CNT4_INTR     ((volatile un_TCPWM_GRP_CNT_INTR_t*) 0x40388270UL)
#define CYREG_TCPWM0_GRP1_CNT4_INTR_SET ((volatile un_TCPWM_GRP_CNT_INTR_SET_t*) 0x40388274UL)
#define CYREG_TCPWM0_GRP1_CNT4_INTR_MASK ((volatile un_TCPWM_GRP_CNT_INTR_MASK_t*) 0x40388278UL)
#define CYREG_TCPWM0_GRP1_CNT4_INTR_MASKED ((volatile un_TCPWM_GRP_CNT_INTR_MASKED_t*) 0x4038827CUL)

/**
  * \brief Timer/Counter/PWM Counter Module (TCPWM_GRP_CNT5)
  */
#define CYREG_TCPWM0_GRP1_CNT5_CTRL     ((volatile un_TCPWM_GRP_CNT_CTRL_t*) 0x40388280UL)
#define CYREG_TCPWM0_GRP1_CNT5_STATUS   ((volatile un_TCPWM_GRP_CNT_STATUS_t*) 0x40388284UL)
#define CYREG_TCPWM0_GRP1_CNT5_COUNTER  ((volatile un_TCPWM_GRP_CNT_COUNTER_t*) 0x40388288UL)
#define CYREG_TCPWM0_GRP1_CNT5_CC0      ((volatile un_TCPWM_GRP_CNT_CC0_t*) 0x40388290UL)
#define CYREG_TCPWM0_GRP1_CNT5_CC0_BUFF ((volatile un_TCPWM_GRP_CNT_CC0_BUFF_t*) 0x40388294UL)
#define CYREG_TCPWM0_GRP1_CNT5_CC1      ((volatile un_TCPWM_GRP_CNT_CC1_t*) 0x40388298UL)
#define CYREG_TCPWM0_GRP1_CNT5_CC1_BUFF ((volatile un_TCPWM_GRP_CNT_CC1_BUFF_t*) 0x4038829CUL)
#define CYREG_TCPWM0_GRP1_CNT5_PERIOD   ((volatile un_TCPWM_GRP_CNT_PERIOD_t*) 0x403882A0UL)
#define CYREG_TCPWM0_GRP1_CNT5_PERIOD_BUFF ((volatile un_TCPWM_GRP_CNT_PERIOD_BUFF_t*) 0x403882A4UL)
#define CYREG_TCPWM0_GRP1_CNT5_LINE_SEL ((volatile un_TCPWM_GRP_CNT_LINE_SEL_t*) 0x403882A8UL)
#define CYREG_TCPWM0_GRP1_CNT5_LINE_SEL_BUFF ((volatile un_TCPWM_GRP_CNT_LINE_SEL_BUFF_t*) 0x403882ACUL)
#define CYREG_TCPWM0_GRP1_CNT5_DT       ((volatile un_TCPWM_GRP_CNT_DT_t*) 0x403882B0UL)
#define CYREG_TCPWM0_GRP1_CNT5_TR_CMD   ((volatile un_TCPWM_GRP_CNT_TR_CMD_t*) 0x403882C0UL)
#define CYREG_TCPWM0_GRP1_CNT5_TR_IN_SEL0 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL0_t*) 0x403882C4UL)
#define CYREG_TCPWM0_GRP1_CNT5_TR_IN_SEL1 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL1_t*) 0x403882C8UL)
#define CYREG_TCPWM0_GRP1_CNT5_TR_IN_EDGE_SEL ((volatile un_TCPWM_GRP_CNT_TR_IN_EDGE_SEL_t*) 0x403882CCUL)
#define CYREG_TCPWM0_GRP1_CNT5_TR_PWM_CTRL ((volatile un_TCPWM_GRP_CNT_TR_PWM_CTRL_t*) 0x403882D0UL)
#define CYREG_TCPWM0_GRP1_CNT5_TR_OUT_SEL ((volatile un_TCPWM_GRP_CNT_TR_OUT_SEL_t*) 0x403882D4UL)
#define CYREG_TCPWM0_GRP1_CNT5_INTR     ((volatile un_TCPWM_GRP_CNT_INTR_t*) 0x403882F0UL)
#define CYREG_TCPWM0_GRP1_CNT5_INTR_SET ((volatile un_TCPWM_GRP_CNT_INTR_SET_t*) 0x403882F4UL)
#define CYREG_TCPWM0_GRP1_CNT5_INTR_MASK ((volatile un_TCPWM_GRP_CNT_INTR_MASK_t*) 0x403882F8UL)
#define CYREG_TCPWM0_GRP1_CNT5_INTR_MASKED ((volatile un_TCPWM_GRP_CNT_INTR_MASKED_t*) 0x403882FCUL)

/**
  * \brief Timer/Counter/PWM Counter Module (TCPWM_GRP_CNT6)
  */
#define CYREG_TCPWM0_GRP1_CNT6_CTRL     ((volatile un_TCPWM_GRP_CNT_CTRL_t*) 0x40388300UL)
#define CYREG_TCPWM0_GRP1_CNT6_STATUS   ((volatile un_TCPWM_GRP_CNT_STATUS_t*) 0x40388304UL)
#define CYREG_TCPWM0_GRP1_CNT6_COUNTER  ((volatile un_TCPWM_GRP_CNT_COUNTER_t*) 0x40388308UL)
#define CYREG_TCPWM0_GRP1_CNT6_CC0      ((volatile un_TCPWM_GRP_CNT_CC0_t*) 0x40388310UL)
#define CYREG_TCPWM0_GRP1_CNT6_CC0_BUFF ((volatile un_TCPWM_GRP_CNT_CC0_BUFF_t*) 0x40388314UL)
#define CYREG_TCPWM0_GRP1_CNT6_CC1      ((volatile un_TCPWM_GRP_CNT_CC1_t*) 0x40388318UL)
#define CYREG_TCPWM0_GRP1_CNT6_CC1_BUFF ((volatile un_TCPWM_GRP_CNT_CC1_BUFF_t*) 0x4038831CUL)
#define CYREG_TCPWM0_GRP1_CNT6_PERIOD   ((volatile un_TCPWM_GRP_CNT_PERIOD_t*) 0x40388320UL)
#define CYREG_TCPWM0_GRP1_CNT6_PERIOD_BUFF ((volatile un_TCPWM_GRP_CNT_PERIOD_BUFF_t*) 0x40388324UL)
#define CYREG_TCPWM0_GRP1_CNT6_LINE_SEL ((volatile un_TCPWM_GRP_CNT_LINE_SEL_t*) 0x40388328UL)
#define CYREG_TCPWM0_GRP1_CNT6_LINE_SEL_BUFF ((volatile un_TCPWM_GRP_CNT_LINE_SEL_BUFF_t*) 0x4038832CUL)
#define CYREG_TCPWM0_GRP1_CNT6_DT       ((volatile un_TCPWM_GRP_CNT_DT_t*) 0x40388330UL)
#define CYREG_TCPWM0_GRP1_CNT6_TR_CMD   ((volatile un_TCPWM_GRP_CNT_TR_CMD_t*) 0x40388340UL)
#define CYREG_TCPWM0_GRP1_CNT6_TR_IN_SEL0 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL0_t*) 0x40388344UL)
#define CYREG_TCPWM0_GRP1_CNT6_TR_IN_SEL1 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL1_t*) 0x40388348UL)
#define CYREG_TCPWM0_GRP1_CNT6_TR_IN_EDGE_SEL ((volatile un_TCPWM_GRP_CNT_TR_IN_EDGE_SEL_t*) 0x4038834CUL)
#define CYREG_TCPWM0_GRP1_CNT6_TR_PWM_CTRL ((volatile un_TCPWM_GRP_CNT_TR_PWM_CTRL_t*) 0x40388350UL)
#define CYREG_TCPWM0_GRP1_CNT6_TR_OUT_SEL ((volatile un_TCPWM_GRP_CNT_TR_OUT_SEL_t*) 0x40388354UL)
#define CYREG_TCPWM0_GRP1_CNT6_INTR     ((volatile un_TCPWM_GRP_CNT_INTR_t*) 0x40388370UL)
#define CYREG_TCPWM0_GRP1_CNT6_INTR_SET ((volatile un_TCPWM_GRP_CNT_INTR_SET_t*) 0x40388374UL)
#define CYREG_TCPWM0_GRP1_CNT6_INTR_MASK ((volatile un_TCPWM_GRP_CNT_INTR_MASK_t*) 0x40388378UL)
#define CYREG_TCPWM0_GRP1_CNT6_INTR_MASKED ((volatile un_TCPWM_GRP_CNT_INTR_MASKED_t*) 0x4038837CUL)

/**
  * \brief Timer/Counter/PWM Counter Module (TCPWM_GRP_CNT7)
  */
#define CYREG_TCPWM0_GRP1_CNT7_CTRL     ((volatile un_TCPWM_GRP_CNT_CTRL_t*) 0x40388380UL)
#define CYREG_TCPWM0_GRP1_CNT7_STATUS   ((volatile un_TCPWM_GRP_CNT_STATUS_t*) 0x40388384UL)
#define CYREG_TCPWM0_GRP1_CNT7_COUNTER  ((volatile un_TCPWM_GRP_CNT_COUNTER_t*) 0x40388388UL)
#define CYREG_TCPWM0_GRP1_CNT7_CC0      ((volatile un_TCPWM_GRP_CNT_CC0_t*) 0x40388390UL)
#define CYREG_TCPWM0_GRP1_CNT7_CC0_BUFF ((volatile un_TCPWM_GRP_CNT_CC0_BUFF_t*) 0x40388394UL)
#define CYREG_TCPWM0_GRP1_CNT7_CC1      ((volatile un_TCPWM_GRP_CNT_CC1_t*) 0x40388398UL)
#define CYREG_TCPWM0_GRP1_CNT7_CC1_BUFF ((volatile un_TCPWM_GRP_CNT_CC1_BUFF_t*) 0x4038839CUL)
#define CYREG_TCPWM0_GRP1_CNT7_PERIOD   ((volatile un_TCPWM_GRP_CNT_PERIOD_t*) 0x403883A0UL)
#define CYREG_TCPWM0_GRP1_CNT7_PERIOD_BUFF ((volatile un_TCPWM_GRP_CNT_PERIOD_BUFF_t*) 0x403883A4UL)
#define CYREG_TCPWM0_GRP1_CNT7_LINE_SEL ((volatile un_TCPWM_GRP_CNT_LINE_SEL_t*) 0x403883A8UL)
#define CYREG_TCPWM0_GRP1_CNT7_LINE_SEL_BUFF ((volatile un_TCPWM_GRP_CNT_LINE_SEL_BUFF_t*) 0x403883ACUL)
#define CYREG_TCPWM0_GRP1_CNT7_DT       ((volatile un_TCPWM_GRP_CNT_DT_t*) 0x403883B0UL)
#define CYREG_TCPWM0_GRP1_CNT7_TR_CMD   ((volatile un_TCPWM_GRP_CNT_TR_CMD_t*) 0x403883C0UL)
#define CYREG_TCPWM0_GRP1_CNT7_TR_IN_SEL0 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL0_t*) 0x403883C4UL)
#define CYREG_TCPWM0_GRP1_CNT7_TR_IN_SEL1 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL1_t*) 0x403883C8UL)
#define CYREG_TCPWM0_GRP1_CNT7_TR_IN_EDGE_SEL ((volatile un_TCPWM_GRP_CNT_TR_IN_EDGE_SEL_t*) 0x403883CCUL)
#define CYREG_TCPWM0_GRP1_CNT7_TR_PWM_CTRL ((volatile un_TCPWM_GRP_CNT_TR_PWM_CTRL_t*) 0x403883D0UL)
#define CYREG_TCPWM0_GRP1_CNT7_TR_OUT_SEL ((volatile un_TCPWM_GRP_CNT_TR_OUT_SEL_t*) 0x403883D4UL)
#define CYREG_TCPWM0_GRP1_CNT7_INTR     ((volatile un_TCPWM_GRP_CNT_INTR_t*) 0x403883F0UL)
#define CYREG_TCPWM0_GRP1_CNT7_INTR_SET ((volatile un_TCPWM_GRP_CNT_INTR_SET_t*) 0x403883F4UL)
#define CYREG_TCPWM0_GRP1_CNT7_INTR_MASK ((volatile un_TCPWM_GRP_CNT_INTR_MASK_t*) 0x403883F8UL)
#define CYREG_TCPWM0_GRP1_CNT7_INTR_MASKED ((volatile un_TCPWM_GRP_CNT_INTR_MASKED_t*) 0x403883FCUL)

/**
  * \brief Timer/Counter/PWM Counter Module (TCPWM_GRP_CNT8)
  */
#define CYREG_TCPWM0_GRP1_CNT8_CTRL     ((volatile un_TCPWM_GRP_CNT_CTRL_t*) 0x40388400UL)
#define CYREG_TCPWM0_GRP1_CNT8_STATUS   ((volatile un_TCPWM_GRP_CNT_STATUS_t*) 0x40388404UL)
#define CYREG_TCPWM0_GRP1_CNT8_COUNTER  ((volatile un_TCPWM_GRP_CNT_COUNTER_t*) 0x40388408UL)
#define CYREG_TCPWM0_GRP1_CNT8_CC0      ((volatile un_TCPWM_GRP_CNT_CC0_t*) 0x40388410UL)
#define CYREG_TCPWM0_GRP1_CNT8_CC0_BUFF ((volatile un_TCPWM_GRP_CNT_CC0_BUFF_t*) 0x40388414UL)
#define CYREG_TCPWM0_GRP1_CNT8_CC1      ((volatile un_TCPWM_GRP_CNT_CC1_t*) 0x40388418UL)
#define CYREG_TCPWM0_GRP1_CNT8_CC1_BUFF ((volatile un_TCPWM_GRP_CNT_CC1_BUFF_t*) 0x4038841CUL)
#define CYREG_TCPWM0_GRP1_CNT8_PERIOD   ((volatile un_TCPWM_GRP_CNT_PERIOD_t*) 0x40388420UL)
#define CYREG_TCPWM0_GRP1_CNT8_PERIOD_BUFF ((volatile un_TCPWM_GRP_CNT_PERIOD_BUFF_t*) 0x40388424UL)
#define CYREG_TCPWM0_GRP1_CNT8_LINE_SEL ((volatile un_TCPWM_GRP_CNT_LINE_SEL_t*) 0x40388428UL)
#define CYREG_TCPWM0_GRP1_CNT8_LINE_SEL_BUFF ((volatile un_TCPWM_GRP_CNT_LINE_SEL_BUFF_t*) 0x4038842CUL)
#define CYREG_TCPWM0_GRP1_CNT8_DT       ((volatile un_TCPWM_GRP_CNT_DT_t*) 0x40388430UL)
#define CYREG_TCPWM0_GRP1_CNT8_TR_CMD   ((volatile un_TCPWM_GRP_CNT_TR_CMD_t*) 0x40388440UL)
#define CYREG_TCPWM0_GRP1_CNT8_TR_IN_SEL0 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL0_t*) 0x40388444UL)
#define CYREG_TCPWM0_GRP1_CNT8_TR_IN_SEL1 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL1_t*) 0x40388448UL)
#define CYREG_TCPWM0_GRP1_CNT8_TR_IN_EDGE_SEL ((volatile un_TCPWM_GRP_CNT_TR_IN_EDGE_SEL_t*) 0x4038844CUL)
#define CYREG_TCPWM0_GRP1_CNT8_TR_PWM_CTRL ((volatile un_TCPWM_GRP_CNT_TR_PWM_CTRL_t*) 0x40388450UL)
#define CYREG_TCPWM0_GRP1_CNT8_TR_OUT_SEL ((volatile un_TCPWM_GRP_CNT_TR_OUT_SEL_t*) 0x40388454UL)
#define CYREG_TCPWM0_GRP1_CNT8_INTR     ((volatile un_TCPWM_GRP_CNT_INTR_t*) 0x40388470UL)
#define CYREG_TCPWM0_GRP1_CNT8_INTR_SET ((volatile un_TCPWM_GRP_CNT_INTR_SET_t*) 0x40388474UL)
#define CYREG_TCPWM0_GRP1_CNT8_INTR_MASK ((volatile un_TCPWM_GRP_CNT_INTR_MASK_t*) 0x40388478UL)
#define CYREG_TCPWM0_GRP1_CNT8_INTR_MASKED ((volatile un_TCPWM_GRP_CNT_INTR_MASKED_t*) 0x4038847CUL)

/**
  * \brief Timer/Counter/PWM Counter Module (TCPWM_GRP_CNT9)
  */
#define CYREG_TCPWM0_GRP1_CNT9_CTRL     ((volatile un_TCPWM_GRP_CNT_CTRL_t*) 0x40388480UL)
#define CYREG_TCPWM0_GRP1_CNT9_STATUS   ((volatile un_TCPWM_GRP_CNT_STATUS_t*) 0x40388484UL)
#define CYREG_TCPWM0_GRP1_CNT9_COUNTER  ((volatile un_TCPWM_GRP_CNT_COUNTER_t*) 0x40388488UL)
#define CYREG_TCPWM0_GRP1_CNT9_CC0      ((volatile un_TCPWM_GRP_CNT_CC0_t*) 0x40388490UL)
#define CYREG_TCPWM0_GRP1_CNT9_CC0_BUFF ((volatile un_TCPWM_GRP_CNT_CC0_BUFF_t*) 0x40388494UL)
#define CYREG_TCPWM0_GRP1_CNT9_CC1      ((volatile un_TCPWM_GRP_CNT_CC1_t*) 0x40388498UL)
#define CYREG_TCPWM0_GRP1_CNT9_CC1_BUFF ((volatile un_TCPWM_GRP_CNT_CC1_BUFF_t*) 0x4038849CUL)
#define CYREG_TCPWM0_GRP1_CNT9_PERIOD   ((volatile un_TCPWM_GRP_CNT_PERIOD_t*) 0x403884A0UL)
#define CYREG_TCPWM0_GRP1_CNT9_PERIOD_BUFF ((volatile un_TCPWM_GRP_CNT_PERIOD_BUFF_t*) 0x403884A4UL)
#define CYREG_TCPWM0_GRP1_CNT9_LINE_SEL ((volatile un_TCPWM_GRP_CNT_LINE_SEL_t*) 0x403884A8UL)
#define CYREG_TCPWM0_GRP1_CNT9_LINE_SEL_BUFF ((volatile un_TCPWM_GRP_CNT_LINE_SEL_BUFF_t*) 0x403884ACUL)
#define CYREG_TCPWM0_GRP1_CNT9_DT       ((volatile un_TCPWM_GRP_CNT_DT_t*) 0x403884B0UL)
#define CYREG_TCPWM0_GRP1_CNT9_TR_CMD   ((volatile un_TCPWM_GRP_CNT_TR_CMD_t*) 0x403884C0UL)
#define CYREG_TCPWM0_GRP1_CNT9_TR_IN_SEL0 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL0_t*) 0x403884C4UL)
#define CYREG_TCPWM0_GRP1_CNT9_TR_IN_SEL1 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL1_t*) 0x403884C8UL)
#define CYREG_TCPWM0_GRP1_CNT9_TR_IN_EDGE_SEL ((volatile un_TCPWM_GRP_CNT_TR_IN_EDGE_SEL_t*) 0x403884CCUL)
#define CYREG_TCPWM0_GRP1_CNT9_TR_PWM_CTRL ((volatile un_TCPWM_GRP_CNT_TR_PWM_CTRL_t*) 0x403884D0UL)
#define CYREG_TCPWM0_GRP1_CNT9_TR_OUT_SEL ((volatile un_TCPWM_GRP_CNT_TR_OUT_SEL_t*) 0x403884D4UL)
#define CYREG_TCPWM0_GRP1_CNT9_INTR     ((volatile un_TCPWM_GRP_CNT_INTR_t*) 0x403884F0UL)
#define CYREG_TCPWM0_GRP1_CNT9_INTR_SET ((volatile un_TCPWM_GRP_CNT_INTR_SET_t*) 0x403884F4UL)
#define CYREG_TCPWM0_GRP1_CNT9_INTR_MASK ((volatile un_TCPWM_GRP_CNT_INTR_MASK_t*) 0x403884F8UL)
#define CYREG_TCPWM0_GRP1_CNT9_INTR_MASKED ((volatile un_TCPWM_GRP_CNT_INTR_MASKED_t*) 0x403884FCUL)

/**
  * \brief Timer/Counter/PWM Counter Module (TCPWM_GRP_CNT10)
  */
#define CYREG_TCPWM0_GRP1_CNT10_CTRL    ((volatile un_TCPWM_GRP_CNT_CTRL_t*) 0x40388500UL)
#define CYREG_TCPWM0_GRP1_CNT10_STATUS  ((volatile un_TCPWM_GRP_CNT_STATUS_t*) 0x40388504UL)
#define CYREG_TCPWM0_GRP1_CNT10_COUNTER ((volatile un_TCPWM_GRP_CNT_COUNTER_t*) 0x40388508UL)
#define CYREG_TCPWM0_GRP1_CNT10_CC0     ((volatile un_TCPWM_GRP_CNT_CC0_t*) 0x40388510UL)
#define CYREG_TCPWM0_GRP1_CNT10_CC0_BUFF ((volatile un_TCPWM_GRP_CNT_CC0_BUFF_t*) 0x40388514UL)
#define CYREG_TCPWM0_GRP1_CNT10_CC1     ((volatile un_TCPWM_GRP_CNT_CC1_t*) 0x40388518UL)
#define CYREG_TCPWM0_GRP1_CNT10_CC1_BUFF ((volatile un_TCPWM_GRP_CNT_CC1_BUFF_t*) 0x4038851CUL)
#define CYREG_TCPWM0_GRP1_CNT10_PERIOD  ((volatile un_TCPWM_GRP_CNT_PERIOD_t*) 0x40388520UL)
#define CYREG_TCPWM0_GRP1_CNT10_PERIOD_BUFF ((volatile un_TCPWM_GRP_CNT_PERIOD_BUFF_t*) 0x40388524UL)
#define CYREG_TCPWM0_GRP1_CNT10_LINE_SEL ((volatile un_TCPWM_GRP_CNT_LINE_SEL_t*) 0x40388528UL)
#define CYREG_TCPWM0_GRP1_CNT10_LINE_SEL_BUFF ((volatile un_TCPWM_GRP_CNT_LINE_SEL_BUFF_t*) 0x4038852CUL)
#define CYREG_TCPWM0_GRP1_CNT10_DT      ((volatile un_TCPWM_GRP_CNT_DT_t*) 0x40388530UL)
#define CYREG_TCPWM0_GRP1_CNT10_TR_CMD  ((volatile un_TCPWM_GRP_CNT_TR_CMD_t*) 0x40388540UL)
#define CYREG_TCPWM0_GRP1_CNT10_TR_IN_SEL0 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL0_t*) 0x40388544UL)
#define CYREG_TCPWM0_GRP1_CNT10_TR_IN_SEL1 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL1_t*) 0x40388548UL)
#define CYREG_TCPWM0_GRP1_CNT10_TR_IN_EDGE_SEL ((volatile un_TCPWM_GRP_CNT_TR_IN_EDGE_SEL_t*) 0x4038854CUL)
#define CYREG_TCPWM0_GRP1_CNT10_TR_PWM_CTRL ((volatile un_TCPWM_GRP_CNT_TR_PWM_CTRL_t*) 0x40388550UL)
#define CYREG_TCPWM0_GRP1_CNT10_TR_OUT_SEL ((volatile un_TCPWM_GRP_CNT_TR_OUT_SEL_t*) 0x40388554UL)
#define CYREG_TCPWM0_GRP1_CNT10_INTR    ((volatile un_TCPWM_GRP_CNT_INTR_t*) 0x40388570UL)
#define CYREG_TCPWM0_GRP1_CNT10_INTR_SET ((volatile un_TCPWM_GRP_CNT_INTR_SET_t*) 0x40388574UL)
#define CYREG_TCPWM0_GRP1_CNT10_INTR_MASK ((volatile un_TCPWM_GRP_CNT_INTR_MASK_t*) 0x40388578UL)
#define CYREG_TCPWM0_GRP1_CNT10_INTR_MASKED ((volatile un_TCPWM_GRP_CNT_INTR_MASKED_t*) 0x4038857CUL)

/**
  * \brief Timer/Counter/PWM Counter Module (TCPWM_GRP_CNT11)
  */
#define CYREG_TCPWM0_GRP1_CNT11_CTRL    ((volatile un_TCPWM_GRP_CNT_CTRL_t*) 0x40388580UL)
#define CYREG_TCPWM0_GRP1_CNT11_STATUS  ((volatile un_TCPWM_GRP_CNT_STATUS_t*) 0x40388584UL)
#define CYREG_TCPWM0_GRP1_CNT11_COUNTER ((volatile un_TCPWM_GRP_CNT_COUNTER_t*) 0x40388588UL)
#define CYREG_TCPWM0_GRP1_CNT11_CC0     ((volatile un_TCPWM_GRP_CNT_CC0_t*) 0x40388590UL)
#define CYREG_TCPWM0_GRP1_CNT11_CC0_BUFF ((volatile un_TCPWM_GRP_CNT_CC0_BUFF_t*) 0x40388594UL)
#define CYREG_TCPWM0_GRP1_CNT11_CC1     ((volatile un_TCPWM_GRP_CNT_CC1_t*) 0x40388598UL)
#define CYREG_TCPWM0_GRP1_CNT11_CC1_BUFF ((volatile un_TCPWM_GRP_CNT_CC1_BUFF_t*) 0x4038859CUL)
#define CYREG_TCPWM0_GRP1_CNT11_PERIOD  ((volatile un_TCPWM_GRP_CNT_PERIOD_t*) 0x403885A0UL)
#define CYREG_TCPWM0_GRP1_CNT11_PERIOD_BUFF ((volatile un_TCPWM_GRP_CNT_PERIOD_BUFF_t*) 0x403885A4UL)
#define CYREG_TCPWM0_GRP1_CNT11_LINE_SEL ((volatile un_TCPWM_GRP_CNT_LINE_SEL_t*) 0x403885A8UL)
#define CYREG_TCPWM0_GRP1_CNT11_LINE_SEL_BUFF ((volatile un_TCPWM_GRP_CNT_LINE_SEL_BUFF_t*) 0x403885ACUL)
#define CYREG_TCPWM0_GRP1_CNT11_DT      ((volatile un_TCPWM_GRP_CNT_DT_t*) 0x403885B0UL)
#define CYREG_TCPWM0_GRP1_CNT11_TR_CMD  ((volatile un_TCPWM_GRP_CNT_TR_CMD_t*) 0x403885C0UL)
#define CYREG_TCPWM0_GRP1_CNT11_TR_IN_SEL0 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL0_t*) 0x403885C4UL)
#define CYREG_TCPWM0_GRP1_CNT11_TR_IN_SEL1 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL1_t*) 0x403885C8UL)
#define CYREG_TCPWM0_GRP1_CNT11_TR_IN_EDGE_SEL ((volatile un_TCPWM_GRP_CNT_TR_IN_EDGE_SEL_t*) 0x403885CCUL)
#define CYREG_TCPWM0_GRP1_CNT11_TR_PWM_CTRL ((volatile un_TCPWM_GRP_CNT_TR_PWM_CTRL_t*) 0x403885D0UL)
#define CYREG_TCPWM0_GRP1_CNT11_TR_OUT_SEL ((volatile un_TCPWM_GRP_CNT_TR_OUT_SEL_t*) 0x403885D4UL)
#define CYREG_TCPWM0_GRP1_CNT11_INTR    ((volatile un_TCPWM_GRP_CNT_INTR_t*) 0x403885F0UL)
#define CYREG_TCPWM0_GRP1_CNT11_INTR_SET ((volatile un_TCPWM_GRP_CNT_INTR_SET_t*) 0x403885F4UL)
#define CYREG_TCPWM0_GRP1_CNT11_INTR_MASK ((volatile un_TCPWM_GRP_CNT_INTR_MASK_t*) 0x403885F8UL)
#define CYREG_TCPWM0_GRP1_CNT11_INTR_MASKED ((volatile un_TCPWM_GRP_CNT_INTR_MASKED_t*) 0x403885FCUL)

/**
  * \brief Timer/Counter/PWM Counter Module (TCPWM_GRP_CNT0)
  */
#define CYREG_TCPWM0_GRP2_CNT0_CTRL     ((volatile un_TCPWM_GRP_CNT_CTRL_t*) 0x40390000UL)
#define CYREG_TCPWM0_GRP2_CNT0_STATUS   ((volatile un_TCPWM_GRP_CNT_STATUS_t*) 0x40390004UL)
#define CYREG_TCPWM0_GRP2_CNT0_COUNTER  ((volatile un_TCPWM_GRP_CNT_COUNTER_t*) 0x40390008UL)
#define CYREG_TCPWM0_GRP2_CNT0_CC0      ((volatile un_TCPWM_GRP_CNT_CC0_t*) 0x40390010UL)
#define CYREG_TCPWM0_GRP2_CNT0_CC0_BUFF ((volatile un_TCPWM_GRP_CNT_CC0_BUFF_t*) 0x40390014UL)
#define CYREG_TCPWM0_GRP2_CNT0_CC1      ((volatile un_TCPWM_GRP_CNT_CC1_t*) 0x40390018UL)
#define CYREG_TCPWM0_GRP2_CNT0_CC1_BUFF ((volatile un_TCPWM_GRP_CNT_CC1_BUFF_t*) 0x4039001CUL)
#define CYREG_TCPWM0_GRP2_CNT0_PERIOD   ((volatile un_TCPWM_GRP_CNT_PERIOD_t*) 0x40390020UL)
#define CYREG_TCPWM0_GRP2_CNT0_PERIOD_BUFF ((volatile un_TCPWM_GRP_CNT_PERIOD_BUFF_t*) 0x40390024UL)
#define CYREG_TCPWM0_GRP2_CNT0_DT       ((volatile un_TCPWM_GRP_CNT_DT_t*) 0x40390030UL)
#define CYREG_TCPWM0_GRP2_CNT0_TR_CMD   ((volatile un_TCPWM_GRP_CNT_TR_CMD_t*) 0x40390040UL)
#define CYREG_TCPWM0_GRP2_CNT0_TR_IN_SEL0 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL0_t*) 0x40390044UL)
#define CYREG_TCPWM0_GRP2_CNT0_TR_IN_SEL1 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL1_t*) 0x40390048UL)
#define CYREG_TCPWM0_GRP2_CNT0_TR_IN_EDGE_SEL ((volatile un_TCPWM_GRP_CNT_TR_IN_EDGE_SEL_t*) 0x4039004CUL)
#define CYREG_TCPWM0_GRP2_CNT0_TR_PWM_CTRL ((volatile un_TCPWM_GRP_CNT_TR_PWM_CTRL_t*) 0x40390050UL)
#define CYREG_TCPWM0_GRP2_CNT0_TR_OUT_SEL ((volatile un_TCPWM_GRP_CNT_TR_OUT_SEL_t*) 0x40390054UL)
#define CYREG_TCPWM0_GRP2_CNT0_INTR     ((volatile un_TCPWM_GRP_CNT_INTR_t*) 0x40390070UL)
#define CYREG_TCPWM0_GRP2_CNT0_INTR_SET ((volatile un_TCPWM_GRP_CNT_INTR_SET_t*) 0x40390074UL)
#define CYREG_TCPWM0_GRP2_CNT0_INTR_MASK ((volatile un_TCPWM_GRP_CNT_INTR_MASK_t*) 0x40390078UL)
#define CYREG_TCPWM0_GRP2_CNT0_INTR_MASKED ((volatile un_TCPWM_GRP_CNT_INTR_MASKED_t*) 0x4039007CUL)

/**
  * \brief Timer/Counter/PWM Counter Module (TCPWM_GRP_CNT1)
  */
#define CYREG_TCPWM0_GRP2_CNT1_CTRL     ((volatile un_TCPWM_GRP_CNT_CTRL_t*) 0x40390080UL)
#define CYREG_TCPWM0_GRP2_CNT1_STATUS   ((volatile un_TCPWM_GRP_CNT_STATUS_t*) 0x40390084UL)
#define CYREG_TCPWM0_GRP2_CNT1_COUNTER  ((volatile un_TCPWM_GRP_CNT_COUNTER_t*) 0x40390088UL)
#define CYREG_TCPWM0_GRP2_CNT1_CC0      ((volatile un_TCPWM_GRP_CNT_CC0_t*) 0x40390090UL)
#define CYREG_TCPWM0_GRP2_CNT1_CC0_BUFF ((volatile un_TCPWM_GRP_CNT_CC0_BUFF_t*) 0x40390094UL)
#define CYREG_TCPWM0_GRP2_CNT1_CC1      ((volatile un_TCPWM_GRP_CNT_CC1_t*) 0x40390098UL)
#define CYREG_TCPWM0_GRP2_CNT1_CC1_BUFF ((volatile un_TCPWM_GRP_CNT_CC1_BUFF_t*) 0x4039009CUL)
#define CYREG_TCPWM0_GRP2_CNT1_PERIOD   ((volatile un_TCPWM_GRP_CNT_PERIOD_t*) 0x403900A0UL)
#define CYREG_TCPWM0_GRP2_CNT1_PERIOD_BUFF ((volatile un_TCPWM_GRP_CNT_PERIOD_BUFF_t*) 0x403900A4UL)
#define CYREG_TCPWM0_GRP2_CNT1_DT       ((volatile un_TCPWM_GRP_CNT_DT_t*) 0x403900B0UL)
#define CYREG_TCPWM0_GRP2_CNT1_TR_CMD   ((volatile un_TCPWM_GRP_CNT_TR_CMD_t*) 0x403900C0UL)
#define CYREG_TCPWM0_GRP2_CNT1_TR_IN_SEL0 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL0_t*) 0x403900C4UL)
#define CYREG_TCPWM0_GRP2_CNT1_TR_IN_SEL1 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL1_t*) 0x403900C8UL)
#define CYREG_TCPWM0_GRP2_CNT1_TR_IN_EDGE_SEL ((volatile un_TCPWM_GRP_CNT_TR_IN_EDGE_SEL_t*) 0x403900CCUL)
#define CYREG_TCPWM0_GRP2_CNT1_TR_PWM_CTRL ((volatile un_TCPWM_GRP_CNT_TR_PWM_CTRL_t*) 0x403900D0UL)
#define CYREG_TCPWM0_GRP2_CNT1_TR_OUT_SEL ((volatile un_TCPWM_GRP_CNT_TR_OUT_SEL_t*) 0x403900D4UL)
#define CYREG_TCPWM0_GRP2_CNT1_INTR     ((volatile un_TCPWM_GRP_CNT_INTR_t*) 0x403900F0UL)
#define CYREG_TCPWM0_GRP2_CNT1_INTR_SET ((volatile un_TCPWM_GRP_CNT_INTR_SET_t*) 0x403900F4UL)
#define CYREG_TCPWM0_GRP2_CNT1_INTR_MASK ((volatile un_TCPWM_GRP_CNT_INTR_MASK_t*) 0x403900F8UL)
#define CYREG_TCPWM0_GRP2_CNT1_INTR_MASKED ((volatile un_TCPWM_GRP_CNT_INTR_MASKED_t*) 0x403900FCUL)

/**
  * \brief Timer/Counter/PWM Counter Module (TCPWM_GRP_CNT2)
  */
#define CYREG_TCPWM0_GRP2_CNT2_CTRL     ((volatile un_TCPWM_GRP_CNT_CTRL_t*) 0x40390100UL)
#define CYREG_TCPWM0_GRP2_CNT2_STATUS   ((volatile un_TCPWM_GRP_CNT_STATUS_t*) 0x40390104UL)
#define CYREG_TCPWM0_GRP2_CNT2_COUNTER  ((volatile un_TCPWM_GRP_CNT_COUNTER_t*) 0x40390108UL)
#define CYREG_TCPWM0_GRP2_CNT2_CC0      ((volatile un_TCPWM_GRP_CNT_CC0_t*) 0x40390110UL)
#define CYREG_TCPWM0_GRP2_CNT2_CC0_BUFF ((volatile un_TCPWM_GRP_CNT_CC0_BUFF_t*) 0x40390114UL)
#define CYREG_TCPWM0_GRP2_CNT2_CC1      ((volatile un_TCPWM_GRP_CNT_CC1_t*) 0x40390118UL)
#define CYREG_TCPWM0_GRP2_CNT2_CC1_BUFF ((volatile un_TCPWM_GRP_CNT_CC1_BUFF_t*) 0x4039011CUL)
#define CYREG_TCPWM0_GRP2_CNT2_PERIOD   ((volatile un_TCPWM_GRP_CNT_PERIOD_t*) 0x40390120UL)
#define CYREG_TCPWM0_GRP2_CNT2_PERIOD_BUFF ((volatile un_TCPWM_GRP_CNT_PERIOD_BUFF_t*) 0x40390124UL)
#define CYREG_TCPWM0_GRP2_CNT2_DT       ((volatile un_TCPWM_GRP_CNT_DT_t*) 0x40390130UL)
#define CYREG_TCPWM0_GRP2_CNT2_TR_CMD   ((volatile un_TCPWM_GRP_CNT_TR_CMD_t*) 0x40390140UL)
#define CYREG_TCPWM0_GRP2_CNT2_TR_IN_SEL0 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL0_t*) 0x40390144UL)
#define CYREG_TCPWM0_GRP2_CNT2_TR_IN_SEL1 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL1_t*) 0x40390148UL)
#define CYREG_TCPWM0_GRP2_CNT2_TR_IN_EDGE_SEL ((volatile un_TCPWM_GRP_CNT_TR_IN_EDGE_SEL_t*) 0x4039014CUL)
#define CYREG_TCPWM0_GRP2_CNT2_TR_PWM_CTRL ((volatile un_TCPWM_GRP_CNT_TR_PWM_CTRL_t*) 0x40390150UL)
#define CYREG_TCPWM0_GRP2_CNT2_TR_OUT_SEL ((volatile un_TCPWM_GRP_CNT_TR_OUT_SEL_t*) 0x40390154UL)
#define CYREG_TCPWM0_GRP2_CNT2_INTR     ((volatile un_TCPWM_GRP_CNT_INTR_t*) 0x40390170UL)
#define CYREG_TCPWM0_GRP2_CNT2_INTR_SET ((volatile un_TCPWM_GRP_CNT_INTR_SET_t*) 0x40390174UL)
#define CYREG_TCPWM0_GRP2_CNT2_INTR_MASK ((volatile un_TCPWM_GRP_CNT_INTR_MASK_t*) 0x40390178UL)
#define CYREG_TCPWM0_GRP2_CNT2_INTR_MASKED ((volatile un_TCPWM_GRP_CNT_INTR_MASKED_t*) 0x4039017CUL)

/**
  * \brief Timer/Counter/PWM Counter Module (TCPWM_GRP_CNT3)
  */
#define CYREG_TCPWM0_GRP2_CNT3_CTRL     ((volatile un_TCPWM_GRP_CNT_CTRL_t*) 0x40390180UL)
#define CYREG_TCPWM0_GRP2_CNT3_STATUS   ((volatile un_TCPWM_GRP_CNT_STATUS_t*) 0x40390184UL)
#define CYREG_TCPWM0_GRP2_CNT3_COUNTER  ((volatile un_TCPWM_GRP_CNT_COUNTER_t*) 0x40390188UL)
#define CYREG_TCPWM0_GRP2_CNT3_CC0      ((volatile un_TCPWM_GRP_CNT_CC0_t*) 0x40390190UL)
#define CYREG_TCPWM0_GRP2_CNT3_CC0_BUFF ((volatile un_TCPWM_GRP_CNT_CC0_BUFF_t*) 0x40390194UL)
#define CYREG_TCPWM0_GRP2_CNT3_CC1      ((volatile un_TCPWM_GRP_CNT_CC1_t*) 0x40390198UL)
#define CYREG_TCPWM0_GRP2_CNT3_CC1_BUFF ((volatile un_TCPWM_GRP_CNT_CC1_BUFF_t*) 0x4039019CUL)
#define CYREG_TCPWM0_GRP2_CNT3_PERIOD   ((volatile un_TCPWM_GRP_CNT_PERIOD_t*) 0x403901A0UL)
#define CYREG_TCPWM0_GRP2_CNT3_PERIOD_BUFF ((volatile un_TCPWM_GRP_CNT_PERIOD_BUFF_t*) 0x403901A4UL)
#define CYREG_TCPWM0_GRP2_CNT3_DT       ((volatile un_TCPWM_GRP_CNT_DT_t*) 0x403901B0UL)
#define CYREG_TCPWM0_GRP2_CNT3_TR_CMD   ((volatile un_TCPWM_GRP_CNT_TR_CMD_t*) 0x403901C0UL)
#define CYREG_TCPWM0_GRP2_CNT3_TR_IN_SEL0 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL0_t*) 0x403901C4UL)
#define CYREG_TCPWM0_GRP2_CNT3_TR_IN_SEL1 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL1_t*) 0x403901C8UL)
#define CYREG_TCPWM0_GRP2_CNT3_TR_IN_EDGE_SEL ((volatile un_TCPWM_GRP_CNT_TR_IN_EDGE_SEL_t*) 0x403901CCUL)
#define CYREG_TCPWM0_GRP2_CNT3_TR_PWM_CTRL ((volatile un_TCPWM_GRP_CNT_TR_PWM_CTRL_t*) 0x403901D0UL)
#define CYREG_TCPWM0_GRP2_CNT3_TR_OUT_SEL ((volatile un_TCPWM_GRP_CNT_TR_OUT_SEL_t*) 0x403901D4UL)
#define CYREG_TCPWM0_GRP2_CNT3_INTR     ((volatile un_TCPWM_GRP_CNT_INTR_t*) 0x403901F0UL)
#define CYREG_TCPWM0_GRP2_CNT3_INTR_SET ((volatile un_TCPWM_GRP_CNT_INTR_SET_t*) 0x403901F4UL)
#define CYREG_TCPWM0_GRP2_CNT3_INTR_MASK ((volatile un_TCPWM_GRP_CNT_INTR_MASK_t*) 0x403901F8UL)
#define CYREG_TCPWM0_GRP2_CNT3_INTR_MASKED ((volatile un_TCPWM_GRP_CNT_INTR_MASKED_t*) 0x403901FCUL)

/**
  * \brief Timer/Counter/PWM Counter Module (TCPWM_GRP_CNT4)
  */
#define CYREG_TCPWM0_GRP2_CNT4_CTRL     ((volatile un_TCPWM_GRP_CNT_CTRL_t*) 0x40390200UL)
#define CYREG_TCPWM0_GRP2_CNT4_STATUS   ((volatile un_TCPWM_GRP_CNT_STATUS_t*) 0x40390204UL)
#define CYREG_TCPWM0_GRP2_CNT4_COUNTER  ((volatile un_TCPWM_GRP_CNT_COUNTER_t*) 0x40390208UL)
#define CYREG_TCPWM0_GRP2_CNT4_CC0      ((volatile un_TCPWM_GRP_CNT_CC0_t*) 0x40390210UL)
#define CYREG_TCPWM0_GRP2_CNT4_CC0_BUFF ((volatile un_TCPWM_GRP_CNT_CC0_BUFF_t*) 0x40390214UL)
#define CYREG_TCPWM0_GRP2_CNT4_CC1      ((volatile un_TCPWM_GRP_CNT_CC1_t*) 0x40390218UL)
#define CYREG_TCPWM0_GRP2_CNT4_CC1_BUFF ((volatile un_TCPWM_GRP_CNT_CC1_BUFF_t*) 0x4039021CUL)
#define CYREG_TCPWM0_GRP2_CNT4_PERIOD   ((volatile un_TCPWM_GRP_CNT_PERIOD_t*) 0x40390220UL)
#define CYREG_TCPWM0_GRP2_CNT4_PERIOD_BUFF ((volatile un_TCPWM_GRP_CNT_PERIOD_BUFF_t*) 0x40390224UL)
#define CYREG_TCPWM0_GRP2_CNT4_DT       ((volatile un_TCPWM_GRP_CNT_DT_t*) 0x40390230UL)
#define CYREG_TCPWM0_GRP2_CNT4_TR_CMD   ((volatile un_TCPWM_GRP_CNT_TR_CMD_t*) 0x40390240UL)
#define CYREG_TCPWM0_GRP2_CNT4_TR_IN_SEL0 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL0_t*) 0x40390244UL)
#define CYREG_TCPWM0_GRP2_CNT4_TR_IN_SEL1 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL1_t*) 0x40390248UL)
#define CYREG_TCPWM0_GRP2_CNT4_TR_IN_EDGE_SEL ((volatile un_TCPWM_GRP_CNT_TR_IN_EDGE_SEL_t*) 0x4039024CUL)
#define CYREG_TCPWM0_GRP2_CNT4_TR_PWM_CTRL ((volatile un_TCPWM_GRP_CNT_TR_PWM_CTRL_t*) 0x40390250UL)
#define CYREG_TCPWM0_GRP2_CNT4_TR_OUT_SEL ((volatile un_TCPWM_GRP_CNT_TR_OUT_SEL_t*) 0x40390254UL)
#define CYREG_TCPWM0_GRP2_CNT4_INTR     ((volatile un_TCPWM_GRP_CNT_INTR_t*) 0x40390270UL)
#define CYREG_TCPWM0_GRP2_CNT4_INTR_SET ((volatile un_TCPWM_GRP_CNT_INTR_SET_t*) 0x40390274UL)
#define CYREG_TCPWM0_GRP2_CNT4_INTR_MASK ((volatile un_TCPWM_GRP_CNT_INTR_MASK_t*) 0x40390278UL)
#define CYREG_TCPWM0_GRP2_CNT4_INTR_MASKED ((volatile un_TCPWM_GRP_CNT_INTR_MASKED_t*) 0x4039027CUL)

/**
  * \brief Timer/Counter/PWM Counter Module (TCPWM_GRP_CNT5)
  */
#define CYREG_TCPWM0_GRP2_CNT5_CTRL     ((volatile un_TCPWM_GRP_CNT_CTRL_t*) 0x40390280UL)
#define CYREG_TCPWM0_GRP2_CNT5_STATUS   ((volatile un_TCPWM_GRP_CNT_STATUS_t*) 0x40390284UL)
#define CYREG_TCPWM0_GRP2_CNT5_COUNTER  ((volatile un_TCPWM_GRP_CNT_COUNTER_t*) 0x40390288UL)
#define CYREG_TCPWM0_GRP2_CNT5_CC0      ((volatile un_TCPWM_GRP_CNT_CC0_t*) 0x40390290UL)
#define CYREG_TCPWM0_GRP2_CNT5_CC0_BUFF ((volatile un_TCPWM_GRP_CNT_CC0_BUFF_t*) 0x40390294UL)
#define CYREG_TCPWM0_GRP2_CNT5_CC1      ((volatile un_TCPWM_GRP_CNT_CC1_t*) 0x40390298UL)
#define CYREG_TCPWM0_GRP2_CNT5_CC1_BUFF ((volatile un_TCPWM_GRP_CNT_CC1_BUFF_t*) 0x4039029CUL)
#define CYREG_TCPWM0_GRP2_CNT5_PERIOD   ((volatile un_TCPWM_GRP_CNT_PERIOD_t*) 0x403902A0UL)
#define CYREG_TCPWM0_GRP2_CNT5_PERIOD_BUFF ((volatile un_TCPWM_GRP_CNT_PERIOD_BUFF_t*) 0x403902A4UL)
#define CYREG_TCPWM0_GRP2_CNT5_DT       ((volatile un_TCPWM_GRP_CNT_DT_t*) 0x403902B0UL)
#define CYREG_TCPWM0_GRP2_CNT5_TR_CMD   ((volatile un_TCPWM_GRP_CNT_TR_CMD_t*) 0x403902C0UL)
#define CYREG_TCPWM0_GRP2_CNT5_TR_IN_SEL0 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL0_t*) 0x403902C4UL)
#define CYREG_TCPWM0_GRP2_CNT5_TR_IN_SEL1 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL1_t*) 0x403902C8UL)
#define CYREG_TCPWM0_GRP2_CNT5_TR_IN_EDGE_SEL ((volatile un_TCPWM_GRP_CNT_TR_IN_EDGE_SEL_t*) 0x403902CCUL)
#define CYREG_TCPWM0_GRP2_CNT5_TR_PWM_CTRL ((volatile un_TCPWM_GRP_CNT_TR_PWM_CTRL_t*) 0x403902D0UL)
#define CYREG_TCPWM0_GRP2_CNT5_TR_OUT_SEL ((volatile un_TCPWM_GRP_CNT_TR_OUT_SEL_t*) 0x403902D4UL)
#define CYREG_TCPWM0_GRP2_CNT5_INTR     ((volatile un_TCPWM_GRP_CNT_INTR_t*) 0x403902F0UL)
#define CYREG_TCPWM0_GRP2_CNT5_INTR_SET ((volatile un_TCPWM_GRP_CNT_INTR_SET_t*) 0x403902F4UL)
#define CYREG_TCPWM0_GRP2_CNT5_INTR_MASK ((volatile un_TCPWM_GRP_CNT_INTR_MASK_t*) 0x403902F8UL)
#define CYREG_TCPWM0_GRP2_CNT5_INTR_MASKED ((volatile un_TCPWM_GRP_CNT_INTR_MASKED_t*) 0x403902FCUL)

/**
  * \brief Timer/Counter/PWM Counter Module (TCPWM_GRP_CNT6)
  */
#define CYREG_TCPWM0_GRP2_CNT6_CTRL     ((volatile un_TCPWM_GRP_CNT_CTRL_t*) 0x40390300UL)
#define CYREG_TCPWM0_GRP2_CNT6_STATUS   ((volatile un_TCPWM_GRP_CNT_STATUS_t*) 0x40390304UL)
#define CYREG_TCPWM0_GRP2_CNT6_COUNTER  ((volatile un_TCPWM_GRP_CNT_COUNTER_t*) 0x40390308UL)
#define CYREG_TCPWM0_GRP2_CNT6_CC0      ((volatile un_TCPWM_GRP_CNT_CC0_t*) 0x40390310UL)
#define CYREG_TCPWM0_GRP2_CNT6_CC0_BUFF ((volatile un_TCPWM_GRP_CNT_CC0_BUFF_t*) 0x40390314UL)
#define CYREG_TCPWM0_GRP2_CNT6_CC1      ((volatile un_TCPWM_GRP_CNT_CC1_t*) 0x40390318UL)
#define CYREG_TCPWM0_GRP2_CNT6_CC1_BUFF ((volatile un_TCPWM_GRP_CNT_CC1_BUFF_t*) 0x4039031CUL)
#define CYREG_TCPWM0_GRP2_CNT6_PERIOD   ((volatile un_TCPWM_GRP_CNT_PERIOD_t*) 0x40390320UL)
#define CYREG_TCPWM0_GRP2_CNT6_PERIOD_BUFF ((volatile un_TCPWM_GRP_CNT_PERIOD_BUFF_t*) 0x40390324UL)
#define CYREG_TCPWM0_GRP2_CNT6_DT       ((volatile un_TCPWM_GRP_CNT_DT_t*) 0x40390330UL)
#define CYREG_TCPWM0_GRP2_CNT6_TR_CMD   ((volatile un_TCPWM_GRP_CNT_TR_CMD_t*) 0x40390340UL)
#define CYREG_TCPWM0_GRP2_CNT6_TR_IN_SEL0 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL0_t*) 0x40390344UL)
#define CYREG_TCPWM0_GRP2_CNT6_TR_IN_SEL1 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL1_t*) 0x40390348UL)
#define CYREG_TCPWM0_GRP2_CNT6_TR_IN_EDGE_SEL ((volatile un_TCPWM_GRP_CNT_TR_IN_EDGE_SEL_t*) 0x4039034CUL)
#define CYREG_TCPWM0_GRP2_CNT6_TR_PWM_CTRL ((volatile un_TCPWM_GRP_CNT_TR_PWM_CTRL_t*) 0x40390350UL)
#define CYREG_TCPWM0_GRP2_CNT6_TR_OUT_SEL ((volatile un_TCPWM_GRP_CNT_TR_OUT_SEL_t*) 0x40390354UL)
#define CYREG_TCPWM0_GRP2_CNT6_INTR     ((volatile un_TCPWM_GRP_CNT_INTR_t*) 0x40390370UL)
#define CYREG_TCPWM0_GRP2_CNT6_INTR_SET ((volatile un_TCPWM_GRP_CNT_INTR_SET_t*) 0x40390374UL)
#define CYREG_TCPWM0_GRP2_CNT6_INTR_MASK ((volatile un_TCPWM_GRP_CNT_INTR_MASK_t*) 0x40390378UL)
#define CYREG_TCPWM0_GRP2_CNT6_INTR_MASKED ((volatile un_TCPWM_GRP_CNT_INTR_MASKED_t*) 0x4039037CUL)

/**
  * \brief Timer/Counter/PWM Counter Module (TCPWM_GRP_CNT7)
  */
#define CYREG_TCPWM0_GRP2_CNT7_CTRL     ((volatile un_TCPWM_GRP_CNT_CTRL_t*) 0x40390380UL)
#define CYREG_TCPWM0_GRP2_CNT7_STATUS   ((volatile un_TCPWM_GRP_CNT_STATUS_t*) 0x40390384UL)
#define CYREG_TCPWM0_GRP2_CNT7_COUNTER  ((volatile un_TCPWM_GRP_CNT_COUNTER_t*) 0x40390388UL)
#define CYREG_TCPWM0_GRP2_CNT7_CC0      ((volatile un_TCPWM_GRP_CNT_CC0_t*) 0x40390390UL)
#define CYREG_TCPWM0_GRP2_CNT7_CC0_BUFF ((volatile un_TCPWM_GRP_CNT_CC0_BUFF_t*) 0x40390394UL)
#define CYREG_TCPWM0_GRP2_CNT7_CC1      ((volatile un_TCPWM_GRP_CNT_CC1_t*) 0x40390398UL)
#define CYREG_TCPWM0_GRP2_CNT7_CC1_BUFF ((volatile un_TCPWM_GRP_CNT_CC1_BUFF_t*) 0x4039039CUL)
#define CYREG_TCPWM0_GRP2_CNT7_PERIOD   ((volatile un_TCPWM_GRP_CNT_PERIOD_t*) 0x403903A0UL)
#define CYREG_TCPWM0_GRP2_CNT7_PERIOD_BUFF ((volatile un_TCPWM_GRP_CNT_PERIOD_BUFF_t*) 0x403903A4UL)
#define CYREG_TCPWM0_GRP2_CNT7_DT       ((volatile un_TCPWM_GRP_CNT_DT_t*) 0x403903B0UL)
#define CYREG_TCPWM0_GRP2_CNT7_TR_CMD   ((volatile un_TCPWM_GRP_CNT_TR_CMD_t*) 0x403903C0UL)
#define CYREG_TCPWM0_GRP2_CNT7_TR_IN_SEL0 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL0_t*) 0x403903C4UL)
#define CYREG_TCPWM0_GRP2_CNT7_TR_IN_SEL1 ((volatile un_TCPWM_GRP_CNT_TR_IN_SEL1_t*) 0x403903C8UL)
#define CYREG_TCPWM0_GRP2_CNT7_TR_IN_EDGE_SEL ((volatile un_TCPWM_GRP_CNT_TR_IN_EDGE_SEL_t*) 0x403903CCUL)
#define CYREG_TCPWM0_GRP2_CNT7_TR_PWM_CTRL ((volatile un_TCPWM_GRP_CNT_TR_PWM_CTRL_t*) 0x403903D0UL)
#define CYREG_TCPWM0_GRP2_CNT7_TR_OUT_SEL ((volatile un_TCPWM_GRP_CNT_TR_OUT_SEL_t*) 0x403903D4UL)
#define CYREG_TCPWM0_GRP2_CNT7_INTR     ((volatile un_TCPWM_GRP_CNT_INTR_t*) 0x403903F0UL)
#define CYREG_TCPWM0_GRP2_CNT7_INTR_SET ((volatile un_TCPWM_GRP_CNT_INTR_SET_t*) 0x403903F4UL)
#define CYREG_TCPWM0_GRP2_CNT7_INTR_MASK ((volatile un_TCPWM_GRP_CNT_INTR_MASK_t*) 0x403903F8UL)
#define CYREG_TCPWM0_GRP2_CNT7_INTR_MASKED ((volatile un_TCPWM_GRP_CNT_INTR_MASKED_t*) 0x403903FCUL)

#endif /* _CYREG_TCPWM_H_ */


/* [] END OF FILE */
